Abstract
This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.
Highlights
Emerging spintronic devices, such as spin-valves and domain-wall magnets (DWM), have rekindled significant research interests in novel circuit and architecture design methodologies [1,2]
One of the most important foundations in modern field programmable gate arrays (FPGAs) technology is the concept of Lookup-Table (LUT), which acts as a hardware implementation of K-map that directly performs reconfigurable logic functions
We present the complete circuit of our stochastic-based logic block (SLB) and validate its correct operation with mixed-mode circuit simulations
Summary
Emerging spintronic devices, such as spin-valves and domain-wall magnets (DWM), have rekindled significant research interests in novel circuit and architecture design methodologies [1,2]. As an even more superior alternative to the conventional non-volatile phase-change memory due to its high density and lower power consumption [12,13] Another conceptually appealing approach to directly applying MTJ-CMOS devices is to stack the programming overhead of an FPGA on top of the logic blocks and interconnect layers that would be implemented in a state-of-the-art CMOS technology. Besides the obvious benefit of higher logic density, vertical stacking with a hybrid MTJ-CMOS device can potentially reduce interconnect length, reducing signal path delay and power consumption and offers a possible route to closing the performance gap between FPGAs and cell-based ASICs. the vast majority of these studies have focused on using spintronic devices as storage elements and configuration memory bits, achieving low power dissipation and high speed without making significant changes to the conventional FPGA architecture and circuit design.
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