MIS Capacitors Research Articles

Design points of ferroelectric field-effect transistors for memory and logic applications as investigated by metal-ferroelectric-metal–insulator–semiconductor gate stack structures using Hf0.5Zr0.5O2 films

The potential of ferroelectric field-effect transistors (FeFETs) was investigated in regard to memory and logic applications. Integrating ferroelectric Hf0.5Zr0.5O2 thin films into FETs, we fabricated FeFETs with a metal-ferroelectric-metal–insulator–semiconductor gate stack structure. It was experimentally confirmed that the memory properties and the subthreshold swing behaviors of FeFETs change in accordance with the area ratios of MIS and MFM capacitors. On the basis of these results, design points of FeFETs were studied using the load-line analysis method. In summary, the absolute value of spontaneous polarization of the ferroelectric material is responsible for the memory applications, while the differential of the spontaneous polarization is crucial for the logic applications, respectively.

Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors

The admittance measurements are commonly used for extraction of parameters of the traps located in the gate stack of the metal-insulator-semiconductor structures. The extraction procedures are based on models of the MIS structure, which are usually based on a modified Nicollian-Brews' equivalent circuit but do not comprise charge communication between the traps and the gate electrode. The model proposed in this work includes the traps-to gate tunnel communication and is used to discuss its impact on the capacitance-voltage characteristics of a MIS capacitor with a double-layer insulator gate stack.

Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors

Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leakage through gate oxide reduces memory retention time and reliability of gate dielectric. Knowledge of conduction mechanisms of gate leakage current is essential for the optimization of process conditions to reduce leakage current and determination of suitable operating voltage of flash memory devices. In this work, conduction mechanisms contributing to gate leakage current in SiC MIS capacitors with different gate dielectric are extracted for the entire range of the gate electric field. Space charge limited (SCL) conduction mechanisms either Ohm’s law or trap filled limit process or combination of both are observed to be dominant at the low electric field. Hopping conduction found to be dominating the leakage current when the slope of leakage current changes from the lower value to a higher value. The sequence of mechanisms contributing to gate leakage current from low electric field to high electric field is found to be same in SiO2 annealed in O2 and N2, SiON and Al2O3/SiON stack. The trap filled limit process, trap-assisted tunneling and FN tunneling are dominating the gate leakage current at low, mid and high electric field respectively in all the investigated MIS capacitors.

Thermal analysis of erbium charge storage nanoparticles embedded in organic MIS structure

We report on the self-heating characteristics of fabricated organic MIS structures using rare earth erbium nanoparticle as electrical charge storage elements. The organic MIS structure consists of a semiconductive polymer synthesized by means of doping two non-conductive polymers with an ionic liquid, glycerol. SEM images revealed that the rare earth nanoparticles are charging. A Zeta analyzer was used to determine the size of the nanoparticles with an average diameter size of 92 nm. The capacitance versus voltage hysteresis loops of the MIS structure revealed large window gates with a voltage span of 33 V when a ±20 V sweep scan was performed. FLIR thermograph showed an increase in temperature of 1.3 °C of the MIS structure when connected to an AC power generator at 60 Hz. Doing so increased the time constant of the device by 47% when the device is connected the a power source for 15 min. We also assessed on the relationship of increasing the temperature of the Er nanoparticles increases the amount of charges stored in the MIS capacitor.

Electrical characterization of high k-dielectrics for 4H-SiC MIS devices

We report promising results regarding the possible use of AlN or Al2O3 as a gate dielectric in 4H-SiC MISFETs. The crystalline AlN films are grown by hot wall metal organic chemical vapor deposition (MOCVD) at 1100 °C. The amorphous Al2O3 films are grown by repeated deposition and subsequent low temperature (200 °C) oxidation of thin Al layers using a hot plate. Our investigation shows a very low density of interface traps at the AlN/4H-SiC and the Al2O3/4H-SiC interface estimated from capacitance-voltage (CV) analysis of MIS capacitors. Current-voltage (IV) analysis shows that the breakdown electric field across the AlN or Al2O3 is ∼ 3 MV/cm or ∼ 5 MV/cm respectively. By depositing an additional SiO2 layer by plasma enhanced chemical vapor deposition at 300 °C on top of the AlN or Al2O3 layers, it is possible to increase the breakdown voltage of the MIS capacitors significantly without having pronounced impact on the quality of the AlN/SiC or Al2O3/SiC interfaces.

The composition and interfacial properties of annealed AlN films deposited on 4H-SiC by atomic layer deposition

We have investigated and compared the influence of annealing temperature on composition and interfacial properties of AlN thin films deposited on 4H-SiC substrates by atomic layer deposition using trimethylaluminum (TMA) and ammonia as precursors at 400 °C. Those as-deposited films were annealed by rapid thermal annealing at 700 °C, 800 °C, 900 °C and 1000 °C for 1 min in N2 atmosphere, respectively. As the annealing temperature increased, the thickness of AlN films decreased and the refractive index increased due to the densification and compositional changes in the films. The roughness of films decreased as the films became denser after annealing. In addition, the deposited AlN film is not amorphous structure and the intensity of the (0002) diffraction of the AlN films enhanced in the annealed films. N-O-Al bond broke down and the intensity of Al-N bond increased with the increase of annealing temperature. Moreover, the interface between AlN and SiC was mainly a transition layer containing Al-O-Si, and the intensity of Al-O-Si was enhanced after annealing at 1000 °C. And the annealing process reduced the negative charge and the density of interface trap of the AlN annealed film in the MIS capacitor. These results provide a significant reference for AlN as a gate dielectric for SiC-based MOS devices in the future.

Electrical properties of 4H-SiC MIS capacitors with AlN gate dielectric grown by MOCVD

We report on the electrical properties of the AlN/4H-SiC interface using capacitance- and conductance-voltage (CV and GV) analysis of AlN/SiC MIS capacitors. The crystalline AlN layers are made by hot wall MOCVD. CV analysis at room temperature reveals an order of magnitude lower density of interface traps at the AlN/SiC interface than at nitrided SiO2/SiC interfaces. Electron trapping in bulk traps within the AlN is significant when the MIS capacitors are biased into accumulation resulting in a large flatband voltage shift towards higher gate voltage. This process is reversible and the electrons are fully released from the AlN layer if depletion bias is applied at elevated temperatures. Current-voltage (IV) analysis reveals that the breakdown electric field intensity across the AlN dielectric is 3–4 MV/cm and is limited by trap assisted leakage. By depositing an additional SiO2 layer on top of the AlN layer, it is possible to increase the breakdown voltage of the MIS capacitors significantly without having much impact on the quality of the AlN/SiC interface.

Kelvin-Probe based carrier-mobility extraction reviewed by finite element simulation

Periodic charging and discharging of an extended metal insulator semiconductor stack from a confined injection contact results in a lateral modulation of the carrier density. It has been demonstrated previously that this redistribution of carriers in the plane of the MIS capacitor is confined to a region near the contacts whose extension relates to the transport properties of the charged channel. Thus, monitoring the surface potential evolution with a Kelvin-Probe gives access to the transport properties of the semiconductor. Here, we investigate on the basis of 2D finite element calculations the rigidity of this proposed method. By using a bipolar drift-diffusion approach, we investigate the impact of the sample geometry, the minority and majority carrier mobility, doping, trapping and the injection properties on the extracted transport parameters. It will be shown that the proposed technique is a reliable method, which gives access to the mobility of the majority carrier species.

Nonlinear impedance spectroscopy of organic MIS capacitors and planar heterojunction diodes

Abstract We present a nonlinear impedance spectroscopy technique and demonstrate its ability to directly measure nonlinear processes including electron-hole recombination and space charge effects in organic-semiconductor-based diodes and MIS capacitors. The method is based on Fourier analysis of the measured higher harmonic current response to an AC voltage signal. Characterization of the higher harmonic response allows nonlinear impedance spectroscopy to measure material and device properties over a wide range of frequencies, which would otherwise be impossible using conventional impedance spectroscopy. As the higher harmonic signals are purely a product of nonlinear processes, they are independent of the linear device capacitance and resistance. This allows space charge and recombination effects to be investigated at several orders of magnitude higher frequency without fitting to an equivalent circuit model.

Effect of post deposition annealing and post metallization annealing on electrical and structural characteristics of Pd/Al2O3/6H-SiC MIS capacitors

PurposeAl2O3 used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.Design/methodology/approachAl2O3 film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N2 at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al2O3/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.FindingsRTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al2O3/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.Originality/valueThe effect of PDA and PMA on the structural and electrical characteristics of Pd/Al2O3/SiC capacitors suitable for flash memory applications is investigated in this paper.

In brief

PAGE 488 Researchers in Korea fabricate a 4-port transverse electromagnetic (TEM) cell to suppress the generation of unwanted EM fields in typical TEM cell devices. The cell is made by introducing transverse slits in the septa of the device, which provide an alternative approach for electromagnetic compatibility (EMC) tests and measurements for many application fields. PAGE 515 A simple approach to improve the Q-factors of MIS capacitors is described in work from Korea. The low conductivity of silicon, as the lower electrode in capacitors, is improved by using a metal electroplating process and adding a Au metal coating. The simple coating process produces capacitors with Q-factors 25 % higher than conventional examples. A 4-port TEM cell for reducing unwanted electromagnetic fields in EMC testing and measurements. PAGE 517 Work from China introduces an analogue phase shifter that is designed to have a wide relative phase shift, low insertion loss and compact size. Simulations and measured results show that it is capable of efficient phase modulation for use in modern microwave systems. Metal electroplating is used to increase the Q factor of MIS capacitors. PAGE 476 Researchers in China propose a methodology for creating ultra-miniaturised frequency selective surfaces (FSSS). They have made single-band and dual-band FSSs with unit cell dimensions of (λ0/34) × (λ0/34) and (λ0/27) × (λ0/27), respectively. The advantages of ultra-miniaturisation, include independent control of filtering performance for different polarisations and extension of the multiband response. Designing phase shifters for modern microwave systems to have a low insertion loss and compact size. PAGE 519 Researchers in Brazil propose an analytical method to determine parameters of photovoltaic cells using explicit equations. The equations allow all parameters of the single diode model to be extracted from data that is provided in photovoltaic panel datasheets. The method is shown to give superior results with lower errors than other reported analytical methods. A methodology for producing single-band and dual-band ultra-miniaturised frequency selective surfaces. Low errors with an analytical method to determine parameters of photovoltaic cells.

Conduction Mechanisms at Interface of AlN/SiN Dielectric Stacks with AlGaN/GaN Heterostructures for Normally-off High Electron Mobility Transistors: Correlating Device Behavior with Nanoscale Interfaces Properties.

In this work, the conduction mechanisms at the interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid metal-insulator-semiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behavior (Vth = +1.2 V), high channel mobility (204 cm2 V-1 s-1), and very good switching behavior (ION/IOFF current ratio of (5-6) × 108 and subthreshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AlN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been compared with a macroscopic temperature-dependent characterization of gate current in MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator and the occurrence of a density of 7 × 108 cm-2 of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated with electrically active defects responsible for the trap-assisted current transport mechanism through the dielectric, observed by the temperature-dependent characterization of the gate current. The results of this study can be relevant for future applications of AlN/SiN bilayers in GaN hybrid MISHEMT technology.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p− substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p− and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Peculiarities of hole trapping in Al2O3-SiO2 gate dielectric stack

Hole trapping was studied in the Al2O3-SiO2 (A-O) dielectric stack developed for HV CMOS and nonvolatile memory (NVM) applications. Pt electrode blocked the electron injection from the gate. Holes tunneling from the p-type Si substrate through the thermal silicon oxide layer (40A) are trapped in the alumina layer (80A) and result in the shift of C-V characteristics of the MIS capacitor. The peculiarities of hole trapping in alumina, investigated to our knowledge for the first time, are reported. The proposed trapping model describes adequately the experimental data. The found empirical expression predicts the drift of device parameters in the chosen operating regimes. The possible applications of A-O stack are discussed.

Capacitance-voltage characterization of Al2O3/GaN-on-insulator (GaNOI) structures with TMAH surface treatment

The capacitance-voltage (C-V) characterizations of Al2O3/GaN-on-insulator (GaNOI) structure, prepared with the Smart Cut™ technology, with and without tetramethylammonium hydroxide (TMAH) surface treatment have been investigated. The GaNOI structure consists of a 150nm-thick GaN layer and a 800μm-thick Si3N4/SiO2 buried insulating layer deposited on sapphire substrate. For fabrication of the MIS capacitor, an Al2O3 layer with thickness of 28nm as a gate dielectric was deposited on the GaNOI wafer by atomic layer deposition (ALD). The calculated carrier concentration of the GaN layer on the buried insulator was increased to 2.8×1017cm−3 from the value of ~5×1016cm−3 for the as-grown undoped GaN layer prior to the wafer transfer. The MIS capacitor with TMAH surface treatment showed a positive threshold voltage shift with negligible hysteresis and low interface trap density compared to the capacitor without TMAH surface treatment. Severe frequency dispersion was observed regardless of the TMAH treatment due to the crystal defects generated during the complicated wafer transfer process.

Improvement in Electrical Characteristics of ALD Al2O3 Film by Microwave Excited Ar/O2 Plasma Treatment

Introduction High-k material is becoming important to manufacture of integrated circuits [1-3]. Especially, Al2O3 is expected for the gate dielectric film of power devices [4] and Metal Insulator Metal (MIM) capacitor [3]. Atomic Layer Deposition (ALD) is an effective method for forming conformal thin dielectric films. In a recent study, using Al2O3 film formed by ALD at low temperature, less variation in the electrical characteristics could be obtained compared with that formed at high temperature [3]. However, large flat-band voltage shift was shown because of low oxidation ability by H2O at low temperature. In order to solve this problem, it is shown that Post Deposition Process (PDP) is an effective way [3]. It is considered that the microwave excited plasma oxidation is candidate for PDP because it has the strong oxidizing capability [5]. However, the electrical characteristics were degraded because the Al2O3/substrate interface was oxidized by the excess strong plasma oxidation in former study [6]. In this paper, we report the effects on the microwave excited Ar/O2 plasma treatment to the electrical characteristics of Al2O3MIS capacitor. ALD and PDP were carried out continuously in the same chamber at low temperature to suppress the oxidation. Experiment MIS capacitors were fabricated on n-type Si(100) wafers with resistivity of 8-12 Ωcm. The active region was formed by thermal oxidation and etching using the buffered HF with surfactant. After the native oxide on the active region was removed by 0.5% diluted HF, 10nm Al2O3 was formed by Trimethylaluminium (TMA)/H2O ALD process at stage temperature of 75oC. The microwave excited Ar/O2 plasma treatment was carried out as PDP just after the ALD-Al2O3 formation in the same chamber. The PDP conditions are as follows: stage temperature was 75oC, process time was 1min, Ar flow rate was 200sccm and 2.45GHz microwave power was 800W. The pressure and O2flow rate at PDP were varied as experimental parameter. We choose the weaker oxidation capability of all PDP conditions than former one [6] in this experiment. Finally, aluminum films were deposited as top and bottom electrode by evaporation. Results and Discussion Figs.1(a) and (b) show C-V characteristics for the case of bias swept negative to positive and positive to negative, respectively. From Fig.1(a), flat-band voltage without PDP is -2.23V. It indicates the existence of positive fixed oxide charges. In all samples with PDP, flat-band voltages are improved (-1.71~-0.95V) and capacitance densities are increased slightly. It is considered that Ar/O2 treatment is effective to improve the quality of Al2O3 film. However, from Fig.1(b), the hysteresis exists regardless of PDP or not. Therefore, the trap density in Al2O3film cannot be completely vanished by these PDP conditions. Figs.2(a) and (b) show I-V characteristics and band diagram when the positive bias is applied to top electrode. Similarly, Figs.3(a) and (b) show ones when the negative bias is applied. Figs.2(a) and 3(a) show that PDP is effective to decrease the leakage current in both bias case. Especially, the leakage current in the negative bias case is lower than positive bias case. These results imply that the Al electrode side of Al2O3 film is intensively improved as shown dark region of Figs.2(b) and 3(b) by Ar/O2 treatment, however, the quality near the Si/Al2O3 interface could not be improved perfectly. It is considered that the PDP is insufficient to improve the interface, and the process condition or the process step should be changed to improve all region of Al2O3film. Conclusion We investigated effects on the microwave excited Ar/O2 plasma treatment to electrical characteristics of Al2O3 MIS capacitor. As a result, using PDP conditions having relatively lower oxidizing ability than the former one [6], we found that the electrical characteristics of Al2O3 film can be improved such as the flat-band voltage (that is the fixed oxide charge), the capacitance density and the leakage current. However, the treatments could not improve the whole Al2O3 film, especially the interface. Therefore, Ar/O2 treatment is effective to improve the quality of Al2O3film, however, more improvement is required. Acknowledgement This work was carried out at fluctuation free facility of New Industry Creation Hatchery Center, Tohoku University. Reference [1] T. hashizume, et al., J. Vac. Sci. Technol. B, 21(2003) 1828 [2] H. Kambayashi, et al., Jpn. Appl. Phys., 52(2013) 04CF09 [3] Y. Koda, et al., ECS Trans., vol.72 (2016) 91-100 [4] P.D. Ye, et al., Appl. Phys. Lett., 86(2005) 06350 [5] T. Ohmi, et al., J. Phys. D: Appl. Phys., 39(2006) R1 [6] T. Suwa, et al., ECS Trans., vol.75 (2016) 207-214 Figure 1

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

Characterization of the Schottky Barrier Height of the Pt/HfO2/p-type Si MIS Capacitor by Internal Photoemission Spectroscopy

Characterization of the Schottky Barrier Height of the Pt/HfO2/p-type Si MIS Capacitor by Internal Photoemission Spectroscopy

Observation of temperature effect on electrical properties of novel Au/Bi0.7Dy0.3FeO3/ZnO/p-Si thin film MIS capacitor for MEMS applications

In this work the dependence of electrical properties on operation temperature (27°C to 200°C) of Au-Cr/Bi0.7Dy0.3FeO3 (BDFO)/ZnO/p-Si (MIS device) are discussed. The thin film of BDFO was deposited by pulsed laser deposition (PLD) on p-Si. From the electrical characterization, the devices properties like ideality factor (η), barrier height) (BH) of Au-Cr/BDFO/ZnO/p-Si MIS were determined. The values of η and BH were found to be 1.34 and 0.86eV at 200°C and 2.16 and 0.30eV; respectively, at room temperature (27°C). The leakage current conduction mechanism of the device was investigated and found to be Schottky emission (SE) in the low electric field (<0.92MVcm−1) regime and trap assisted Poole–Frenkel (PF) mechanism for high electric field regime. The coexistence of ferroelectric and ferromagnetic coupling and excellent dielectric properties in multiferroic BDFO offers potential in the field of memory devices; sensing and energy harvesting (cantilevers).

Oxidizing Species Dependence of the Interface Reaction during Atomic-Layer-Deposition Process and Post-Deposition-Anneal

Introduction Al2O3 film is an attractive gate dielectric material for the power devices [1] and metal-insulator-metal capacitors [2]. For Al2O3 deposition, the atomic layer deposition (ALD) is one of the most promising methods [3]. It is considered that the oxidation is one of the important processes in ALD. In the case of using radical oxidation in ALD, it is suggested by XPS evaluation that the oxidizing reaction is occurred at the Al2O3/Si interface during ALD [4]. In the former study, H2O oxidation at stage temperature of 75 °C was shown to be effective because of not oxidizing Si [4]. However the oxidation ability of H2O becomes low at such low temperature. Therefore, it is required to introduce the post-deposition-annealing (PDA) without oxidizing the interface to improve Al2O3 film quality [4, 5]. In this paper, the characteristics of Al2O3/Si interface formed during ALD and PDA are evaluated by MIS capacitor, and its interface structure was also observed by Rutherford backscattering spectroscopy (RBS) for clarifying the mechanism of its degradation. Experiment MIS capacitors were fabricated on Cz-n Si(100) wafers (8-12 ohm cm). At first, the native oxide on Si surface was removed by diluted HF (0.5%), and after that Al2O3 films (20 nm) were deposited on Si by ALD [4]. Finally, Al-electrodes were formed by the evaporation. The Al2O3 films were prepared with and without PDA. Here, PDA-I and PDA-II were carried out by O2 annealing at 400 oC [5] and Ar/O2 plasma oxidation [6], respectively. For RBS measurement, Co(10 nm)/SiN(5 nm)/Si(100)-substrate were used. SiN was formed by low-pressure thermal CVD at 725 oC on Si substrate, and after that Co was formed by sputtering. Here, Co was used because it is easy to detect the oxidizing reaction at Al2O3/Co interface. Al2O3 films were deposited on Co by 11-cycles-ALD. Here, by 11-cycles-ALD, Al2O3film (3 nm) was deposited on Si. Results and Discussion Figure 1 shows the capacitance-voltage (C-V) curves of MIS capacitors. Four samples for each were measured. In the case of Al2O3 without PDA, flat band voltage (Vfb) is negative value such as around -2.0 V. It is suggested that the positive charges (1.87×1012 cm-2 ~ 2.53×1012 cm-2) exist in Al2O3 film. After PDA-I, Vfb becomes almost same value such as 0.1 V and the negative charges (1.12×1012 cm-2 ~ 1.17×1012 cm-2) exist in Al2O3 film. In addition, Vfb variability drastically decreases. It is considered that O2 annealing at 400 oC is very effective to improve Al2O3 film quality [5]. On the other hand, after PDA-II, Vfb drastically shifts to the positive direction by the negative charges (2.96×1012 cm-2 ~ 8.61×1012 cm-2) and its variability is large. Moreover the slope of C-V curve with PDA-II is smaller than that without PDA because of increasing the interface trap. As a result, it is considered that the interfacial quality became poor by Ar/O2plasma oxidation in this experiment. Figure 2 shows the energy spectra of 450 keV He+ ions backscattered from Al2O3/Co/SiN/Si. Al2O3films without PDA, with PDA-II 20sec, 60sec and 300sec were measured. Several observed peaks indicate the energy of He ions scattered by Co, Al, Si, O and N atoms, respectively. Figure 3 (a)-(c) show the narrow spectra related to O, Al and Co, respectively. Especially, in the case of PDA-II 300 sec, each spectrum in fig. 3(a)-(c) spreads more widely. It is suggested that Al and Co interdiffuse at the interfacial layer during PDA-II 300sec. As a result, it is suggested that the intermediate oxide states consisting of Al-Co-O are formed. Conclusion We investigated the influence of PDA to the Al2O3 interface. O2 annealing at 400 oC is very effective for improving the Al2O3 film quality. However, by Ar/O2 plasma oxidation, it is considered that Al and Co interdiffuse at the interface. It is expected that a similar phenomenon is also caused with Al2O3/Si interface, then it is considered that the intermediate oxide states consisting of Al-Si-O cause the electrical characteristic degradation such as increase of fixed charge, interface trap and variability. Acknowledgments This work was carried out at fluctuation free facility of New Industry Creation Hatchery Center, Tohoku University. Reference [1] P.D. Ye et al., Appl. Phys. Lett., 86(2005) 063501 [2] A. Farcy et al., Microelectronic Eng., 85(2008) 1940-1946 [3] R. L. Puurunen, J. Appl. Phys. 97(2005) 121301 [4] H. Sugita, et al., ECS Trans, 66(2015) 305-314 [5] Y. Koda, et al., ECS Trans., to be published at 229thECS meeting [6] K. Sekine, et al., IEEE TRANS. ON ELECTRON DEVICE, 48 (8) (2001) 1550 Figure 1