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Abstract
The admittance measurements are commonly used for extraction of parameters of the traps located in the gate stack of the metal-insulator-semiconductor structures. The extraction procedures are based on models of the MIS structure, which are usually based on a modified Nicollian-Brews' equivalent circuit but do not comprise charge communication between the traps and the gate electrode. The model proposed in this work includes the traps-to gate tunnel communication and is used to discuss its impact on the capacitance-voltage characteristics of a MIS capacitor with a double-layer insulator gate stack.
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