Peculiarities of hole trapping in Al2O3-SiO2 gate dielectric stack

Abstract

Hole trapping was studied in the Al2O3-SiO2 (A-O) dielectric stack developed for HV CMOS and nonvolatile memory (NVM) applications. Pt electrode blocked the electron injection from the gate. Holes tunneling from the p-type Si substrate through the thermal silicon oxide layer (40A) are trapped in the alumina layer (80A) and result in the shift of C-V characteristics of the MIS capacitor. The peculiarities of hole trapping in alumina, investigated to our knowledge for the first time, are reported. The proposed trapping model describes adequately the experimental data. The found empirical expression predicts the drift of device parameters in the chosen operating regimes. The possible applications of A-O stack are discussed.