Midgap Interface State Density Research Articles

A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching.

Producing densely packed high aspect ratio In0.53Ga0.47As nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III-V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based In0.53Ga0.47As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of InxGa1-xAs is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In0.53Ga0.47As, in contrast to higher bandgap semiconductors (e.g., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In0.53Ga0.47As metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality In0.53Ga0.47As nanostructures that will potentially enable large-volume production of In0.53Ga0.47As-based devices including three-dimensional transistors and high-efficiency infrared photodetectors.

ALD Hf0.2Zr0.8O2and HfO2with cyclic annealing/SPA plasma treatment: reliability

The reliability of atomic layer-deposited Hf0.2Zr0.8O2and HfO2on a SiON interfacial layer (IL) with cyclic deposition and annealing (DADA) and cyclic deposition and slot-plane-antenna Ar plasma exposure (DSDS) is studied. The results are compared with control, that is, As-Deposited samples, without any treatment during or after the dielectric deposition. DSDS Hf0.2Zr0.8O2demonstrates a promising equivalent oxide thickness (EOT) downscaling ability, a reduced gate leakage current, and low mid-gap interface state density as compared to the control device, while DADA Hf0.2Zr0.8O2has degraded the value of EOT as well as a degraded interface. When devices are subjected to a constant voltage stress in the gate injection mode, DSDS Hf0.2Zr0.8O2showed a four times reduction in the flat-band voltage shift and a three order of magnitude reduction in the stress-induced leakage current within 100-s stress as compared to the control sample. The observed time to failure, T63%, is the highest for DSDS Hf0.2Zr0.8O2. The addition of Zr and the cyclic plasma exposure (DSDS process) seems to supress the oxide trap formation in Hf0.2Zr0.8O2films. When DSDS Hf0.2Zr0.8O2deposited on two different ILs, SiON and plasma oxynitride are compared, in that SiON demonstrates improved reliability as compared to plasma oxynitride.

Dielectric Charge Tailoring in PECVD SiO<inline-formula> <tex-math>${}_x$</tex-math> </inline-formula>/SiN <inline-formula> <tex-math>${}_x$</tex-math> </inline-formula> Stacks and Application at the Rear of Al Local Back Surface Field Si Wafer Solar Cells

State-of-the-art surface passivation results are obtained on undiffused p-type commercial-grade Czochralski Si wafers with effective surface recombination velocity S eff values of ∼8 cm/s and implied open-circuit voltage iV oc values of up to 715 mV with an industrially fired dielectric stack of silicon oxide and silicon nitride (SiO ${}_x$ /SiN ${}_x$ ) deposited in an industrial inline plasma-enhanced chemical vapor deposition reactor. We are able to controllably vary the total positive charge density Q total in the stack by more than one order of magnitude (1011–10 12 cm−2) with no impact on midgap interface state density D it,midgap (5 × 1011 eV−1·cm−2) by altering the deposition temperature of the SiO ${}_x$ layer in the stack. We show experimentally that, for inversion conditions, S eff scales with the inverse square of the charge density $1/Q_{{\rm total}}^2$ , which is in good agreement with theory. Based on the measured injection-level–dependent minority carrier lifetimes and the total positive charge densities, it is shown that films with higher positive charge density have higher 1-sun V oc and fill factor ( FF ) potential. Large-area alloyed aluminum local back surface field solar cells confirmed this by showing higher conversion efficiency by 0.17% absolute due to improved cell V oc and FF of the solar cells featuring a SiO ${}_x$ /SiN ${}_x$ stack with a higher Q total.

Characterization of midgap interface states at Al2O3/InAlN interface formed by atomic layer deposition

The midgap interface state density of the Al2O3/In0.19Al0.81N interface formed by atomic layer deposition was investigated by photoassisted capacitance–voltage (C–V) measurement. The interface-state density was derived to be in the range of 1012 eV−1 cm−2 around the midgap. The hysteresis of the C–V curve increased as the irradiated photon energy increased beyond the threshold value of 1.8 eV. This threshold energy value coincided with the energy difference between the conduction band edge and the charge neutrality level ECNL for In0.19Al0.81N, which indicated the density of interface states at around ECNL to be below the detection limit.

Effective interface passivation of a Ge/HfO2 gate stack using ozone pre-gate treatment and ozone ambient annealing

The physical and electrical properties of a Ge/GeO2/HfO2/Al gate stack are investigated. A thin interfacial GeO2 layer (∼1 nm) is formed between Ge and HfO2 by dual ozone treatments, which passivates the Ge/high-k interface. Capacitors on p-type Ge substrates show very promising capacitance-voltage (C—V) characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition, indicating efficient passivation of the Ge/HfO2 interface. It is shown that the mid-gap interface state density atthe Ge/GeO2 interface is 6.4 × 1011 cm−2 · eV−1. In addition, the gate leakage current density of the Ge/GeO2/HfO2/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO2/Al gate stack without interface passivation.

Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV−1 cm−2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V−1 s−1 and 740 cm2 V−1 s−1 at carrier density of 6.5 × 1012 cm−2) for a 1.3 nm EOT.

Thin TiO2 grown by metal–organic chemical vapor deposition on (NH4)2S x -treated InP

The electrical characteristics of thin TiO2 films prepared by metal–organic chemical vapor deposition grown on a p-type InP substrate were studied. For a TiO2 film of 4.7 nm on InP without and with ammonium sulfide treatment, the leakage currents are 8.8×10−2 and 1.1×10−4 A/cm2 at +2 V bias and 1.6×10−1 and 8.3×10−4 A/cm2 at −2 V bias. The lower leakage currents of TiO2 with ammonium sulfide treatment arise from the improvement of interface quality. The dielectric constant and effective oxide charge number density are 33 and 2.5×1013 cm2, respectively. The lowest mid-gap interface state density is around 7.6×1011 cm−2 eV−1. The equivalent oxide thickness is 0.52 nm. The breakdown electric field increases with decreasing thickness in the range of 2.5 to 7.6 nm and reaches 9.3 MV/cm at 2.5 nm.

Low-Temperature Formation of High-Quality $ \hbox{GeO}_{2}$ Interlayer for High-$\kappa$ Gate Dielectrics/Ge by Electron-Cyclotron-Resonance Plasma Techniques

We have fabricated an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-dielectric stack on p-type Ge by electron-cyclotron-resonance plasma oxidation and sputtering without external substrate heating. We show that the midgap interface state density at the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ge interface is 4.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> · eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The hysteresis observed in capacitance-voltage measurements is reduced to 50 mV when the gate bias is swept from accumulation to inversion and back to accumulation or after a single dummy sweep from inversion to accumulation, indicating the possibility that the bulk oxide traps causing the hysteresis are deactivated by the injected holes. The band gap of GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> was determined by internal photoemission measurements to be 4.7 eV. The conduction- and valence-band offsets at the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ge interface are moderately symmetric and large with values of 1.8 and 2.2 eV, respectively. These promising results suggest that low-temperature plasma-grown GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is a suitable interlayer between high-dielectric-constant dielectrics and Ge.

Quantification of metal oxide semiconductor field effect transistor device reliability with low-Vt lanthanum-incorporated high permittivity dielectrics

Results from an extensive reliability characterization of HfLaSiO(N) devices, with TaN gate electrodes, are reported. It is shown that the effect of the lanthanum, initially deposited as La2O3, on a SiO2/HfSiO(N) stack, permeates the Si/SiO2 interface. A lower midgap interface state density is observed at this interface, but increased densities are seen towards the band edges. The presence of lanthanum in the dielectric results in defects in the interface layer and in the high-κ dielectric. A profile of defects in the gate stack is suggested, inferred from a combination of electrical measurements. From the location of the defects, it is argued that the reliability of lanthanum-incorporated devices is not compromised by its presence, thus enabling a reliable route to Vt tuning of n-type metal oxide semiconductor devices.

Oxidant prepulsing of Ge (100) prior to atomic layer deposition of Al2O3: In situ surface characterization

We investigate the effects of H2O oxidant pulsing of Ge (100) substrates prior to Al2O3 atomic layer deposition (ALD) to synthesize metal-oxide-semiconductor devices. The prepulsing reduces the hysteresis in capacitance-voltage measurements from 490 to 30 mV at the flatband voltage and appears to reduce the density of fast interface states while causing a small increase in the midgap interface state density. Real-time x-ray photoelectron spectroscopy during prepulsing revealed the dynamic evolution of Ge–O bonding states and the formation of a surface layer with ∼70% hydroxyl termination which appears to produce a less defective interfacial region after subsequent Al2O3 ALD.

Electrical Properties of $\hbox{Ga}_{2}\hbox{O}_{3}/ \hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of Ga2O3/GaAs interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm (0.9 les EOT les 3.9 nm) have been characterized by capacitance-voltage measurements. Midgap interface state density Dit, effective workfunction phim, fixed charge Qf, dielectric constant kappa, and low field leakage current density are 2 times1011 cm-2 middoteV-1, 4.93 eV, -8.9 times1011 cm-2, 19.5, and 10-9- 10-8 A/cm2, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.

Performance enhancement of n-channel inversion type InxGa1−xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer

Significant enhancement in metal-oxide-semiconductor field effect transistor (MOSFET) transport characteristics is achieved with InxGa1−xAs (x=0.53, x=0.20) channel material using ex situ plasma enhanced chemical vapor deposited amorphous Si layer. InxGa1−xAs MOSFETs (L=2 μm, Vgs-Vt=2.0 V) with Si interlayer show a maximum drain current of 290 mA/mm (x=0.53) and 2 μA/mm (x=0.20), which are much higher compared to devices without a Si interlayer. However, charge pumping measurements show a lower average interface state density near the intrinsic Fermi level for devices without the silicon interlayer indicating that a reduction in the midgap interface state density is not responsible for the improved transport characteristics.

N-Channel GaAs MOSFET with TaN ∕ HfAlO Gate Stack Formed Using In Situ Vacuum Anneal and Silane Passivation

A surface passivation technique for GaAs that comprises in situ vacuum anneal and silane treatment and that is compatible and can be easily integrated with a matured metallorganic chemical vapor deposition high- gate dielectric process module is demonstrated. Extensive investigation of the dependence of electrical characteristics of gate stacks on process conditions, including in situ vacuum anneal and treatment temperatures, postgate-dielectric deposition anneal, and forming gas anneal conditions, is reported. It is shown that excellent capacitance-voltage characteristics with low-frequency dispersion, small hysteresis, and low midgap interface state density of can be achieved with optimum processing conditions. The passivation technique reported here enables the fabrication of a self-aligned n–metal oxide semiconductor field-effect transistor, exhibiting good transfer characteristics with high peak carrier mobility of . The incorporation of and coimplantation for achievement of high dopant activation in deep source and drain (S/D) regions and complementary metal oxide semiconductor compatible gold-free–based PdGe S/D ohmic contacts were also demonstrated.

Compound semiconductor MOSFETs

Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high- κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga 2O 3, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (Gd xGa 1−x) 2O 3 bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 10 11 cm −2 eV −1 and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively.

Development of GaAs-based MOSFET using molecular beam epitaxy

Enhancement mode, high electron mobility PHEMT-based metal oxide semi conductor field effect transistor (MOSFET) devices have been fabricated using an oxide high- κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga 2 O 3 , initially deposited on the surface of the III–V device unpins the GaAs Fermi level while the deposition of a bulk ternary ( Gd x Ga 1 - x ) 2 O 3 layer forms the highly resistive layer to reduce leakage current through the dielectric stack. The use of molecular beam epitaxy allows for the control and uniformity of the oxide layers along the growth direction and deposition conditions were optimized for oxide surface morphology and interface quality. A midgap interface state density for the high- κ stack on GaAs of ≅ 2 × 10 11 cm - 2 eV - 1 and a dielectric constant of κ ≅ 20 are determined using electrical measurements. Enhancement-mode n-channel MOSFETs with a gate length of 1 μ m and a source-drain spacing of 3 μ m show a threshold voltage, saturation current, transconductance, and on-resistance of 0.11 V, 380 mA mm - 1 , 250 mS mm - 1 , and 4.5 Ω mm , respectively.

Unpinned metal gate/high-κ GaAs capacitors: Fabrication and characterization

Fabrication of GaAs metal-oxide-semiconductor capacitors (MOSCAPs) with an unpinned interface is reported. The MOSCAP structure consists of a few monolayers of germanium grown in a molecular beam epitaxy (MBE) system in order to terminate an MBE-grown silicon-doped (100) GaAs layer. An ex situ HfO2 high-κ dielectric with an equivalent oxide thickness of 12Å was deposited by using a dc magnetron sputtering system. A midgap interface state density (Dit) of 5×1011eV−1cm−2 was measured using the high-frequency conductance technique. A rapid thermal annealing study was performed in order to examine the integrity of the gate stack at different temperatures. In addition, a forming gas anneal at 400°C appears to significantly reduce the midgap Dit revealed by probing the frequency dispersion behavior of the MOSCAPs.

Gate dielectric on compound semiconductors by molecular beam epitaxy

An oxide-based high-κ gate dielectric stack for GaAs has been developed using molecular beam epitaxy. A template layer of Ga2O3, initially deposited on a GaAs(001) surface, serves to unpin the GaAs Fermi level while the deposition of a bulk ternary (GdxGa1−x)2O3 layer forms the highly resistive layer to reduce leakage current through the dielectric stack. The use of molecular beam epitaxy allows for the control and uniformity of the oxide layers along the growth direction and deposition conditions were optimized for oxide surface morphology and interface quality. The midgap interface state density for the high-κ stack on GaAs of ≅2×1011cm−2eV−1 and a dielectric constant of k≅20 are determined using electrical measurements. Metal oxide semiconductor field effect transistor layer structures were produced by replacing the GaAs cap layer in a pseudomorphic high electron mobility transistor-type layer structure with the high-κ gate dielectric stack.

Gate dielectrics on compound semiconductors

An oxide-based high-κ gate dielectric for GaAs has been developed using molecular beam epitaxy. A template layer of Ga2O3 is initially deposited on a GaAs(001) surface followed by the deposition of a bulk (GdxGa1−x)2O3 layer. The Ga2O3 layer serves to unpin the GaAs Fermi level while the GdGaO layer forms the high resistive layer to reduce leakage current through the dielectric stack. Deposition conditions during MBE were optimized for oxide surface morphology and interface quality. The use of molecular beam epitaxy also allowed for the control and uniformity of the ternary GdGaO layer along the growth direction. The midgap interface state density for the high-κ stack on GaAs of≅2×1011 cm−2 eV−1, and a dielectric constant of k≅20 were determined using electrical measurements. MOSFET devices were produced by replacing the GaAs cap layer in a PHEMT-type structure with a thick oxide layer. A contactless method was used to determine the mobilities from such devices which were comparable to those measured on a GaAs PHEMT using conventional Hall measurement.

Optical and dielectric properties of gadolinium–indium oxide films prepared on Si (1 0 0) substrate

Samples of thin (Gd–In) oxide film were prepared on quartz and Si(P) substrates for optical and electrical investigations. These samples were annealed at different conditions and characterised by UV–Vis absorption spectroscopy, X-ray fluorescence (XRF) and X-ray diffraction (XRD). The AC-conductance and capacitance were studied as a function of frequency, temperature, and gate voltage. The ‘corrected barrier hopping’ CBH model controls the frequency dependence of the conductivity and capacitance. Good oxide-Si interface properties due to low midgap interface state density was observed for (Gd–In) oxide sample annealed in vacuum.