Midgap Interface State Density Research Articles

Electrical properties of plasma-grown gate oxides on tensile-strained Si 1− y C y alloy

Growth of gate-quality ultrathin (<100 Å) oxides directly on tensile-strained Si1−yCy alloy layers has been investigated using microwave O2-plasma discharge. The electrical properties of oxide grown on an Si0.993C0.007 layer have been studied using a metal-oxide-semiconductor structure. Fixed oxide charge density and mid-gap interface state density are found to be 2.5×1011 cm−2 and 2.0×1011 cm−2 eV−1, respectively. Oxide film exhibits hole trapping behaviour under Fowler–Nordheim constant current stressing.

Stable gallium arsenide MIS capacitors and MIS field effect transistors by (NH/sub 4/)/sub 2/S/sub x/ treatment and hydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH/sub 4/)/sub 2/S/sub x/ chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550/spl deg/C is shown to be the key process for achieving midgap interface state density below 10/sup 11//cm/sup 2//eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH/sub 4/)/sub 2/S/sub x/ treated GaAs substrate using gate dielectrics such as PECVD SiO/sub 2/ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g/sub ms/ measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g/sub ms/ is almost absent in the devices fabricated on (NH/sub 4/)/sub 2/S/sub x/-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH/sub 4/)/sub 2/S/sub x/ treatment.

Swift heavy ion-induced recrysallization of silicon-on-insulator (SOI) structures

Buried Si 3N 4–Si interfaces and overlayer in silicon-on-insulator (SOI) structures were improved by irradiation with 100 MeV 107Ag after the synthesis of buried silicon nitride layers by high dose nitrogen ion-implantation. Auger electron spectroscopy (AES) depth profile analysis illustrates that the MeV heavy ions irradiation in the SOI structure, modifies the distribution of nitrogen that results in better stoichiometry of the buried silicon nitride layers and abrupt Si 3N 4–Si interfaces. Electron spin resonance (ESR) technique shows the improvement in the crystalline structure of the Si over layer. Current–voltage and high frequency capacitance–voltage ( C– V) characteristics were studied, and electrical breakdown measurements were performed on metal nitride silicon (MNS) structures fabricated after removing the Si over layer in the SOI structure. In the ion-beam irradiated SOI specimens, buried silicon nitride layer show a high breakdown field strength of 4.5–6.5 MV/cm as compared to that of 3.0–3.9 MV/cm in the unirradiated one. The C– V analysis of the MNS capacitors reveals that the buried Si 3N 4–Si substrate interface exhibits a better quality with reduced fixed insulator charge and interface state densities after the ion-beam irradiation. Mid-gap interface state density at the buried Si 3N 4–Si substrate interface was as low as 1.0×10 11 cm −2 V −2 after the ion-beam irradiation, which is comparable to that of silicon nitride films deposited on silicon (Si) by the conventional low pressure chemical vapor deposition technique. The role of MeV ion-beam irradiation in improving the properties of SOI structures has been discussed on the basis of various models.

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10−5 A/cm2 at a bias of −1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ∼3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

Hafnium and zirconium silicates for advanced gate dielectrics

Hafnium and zirconium silicate (HfSixOy and ZrSixOy, respectively) gate dielectric films with metal contents ranging from ∼3 to 30 at. % Hf, or 2 to 27 at. % Zr (±1 at. % for Hf and Zr, respectively, within a given film), have been investigated, and films with ∼2–8 at. % Hf or Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness tox of about 18 Å (21 Å) for a 50 Å HfSixOy (50 Å ZrSixOy) film deposited directly on a Si substrate. Current–voltage measurements show for the same films a leakage current of less than 2×10−6 A/cm2 at 1.0 V bias. Hysteresis in these films is measured to be less than 10 mV, the breakdown field is measured to be EBD∼10 MV/cm, and the midgap interface state density is estimated to be Dit∼1–5×1011 cm−2 eV−1. Au electrodes produce excellent electrical properties, while Al electrodes produce very good electrical results, but also react with the silicates, creating a lower ε layer at the metal interface. Transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy indicate that the dielectric films are amorphous silicates, rather than crystalline or phase-separated silicide and oxide structures. TEM shows that these films remain amorphous and stable up to at least 1050 °C in direct contact with Si substrates.

Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon

Hafnium silicate (HfSixOy) gate dielectric films with ∼6 at. % Hf exhibit significantly improved leakage properties over SiO2 in the ultrathin regime while remaining thermally stable in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness (tox) of less than 18 Å for a 50 Å HfSixOy film deposited directly on a Si substrate, with no significant dispersion of the capacitance for frequencies ranging from 10 kHz to 1 MHz. Current–voltage measurements show for the same film a leakage current of 1.2×10−6 A/cm2 at 1 V bias. Hysteresis in these films is measured to be less than 20 mV, the breakdown field is measured to be EBD∼10 MV/cm, and the midgap interface state density is Dit∼1011 cm−2 eV−1. Cross-sectional transmission electron microscopy shows no signs of reaction or crystallization in HfSixOy films on Si after being annealed at 800 °C for 30 min.

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Abstract Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n -type Si(100) substrates. Activation of boron-implanted p + polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n -type substrate was investigated by performing a quasi-static C – V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D it , between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p + poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.

Improvement in buried silicon nitride silicon-on-insulator structures by fluorine-ion implantation

As an effort to improve buried Si3N4–Si interfaces in silicon-on-insulator (SOI) structures, fluorine was implanted either before or after the synthesis of buried silicon nitride layers by high dose nitrogen ion implantation. In these synthesized SOI structures, the thickness of Si overlayer and the buried silicon nitride layer was found to be 2400±25 and 1725±25 Å, respectively. Auger electron spectroscopy depth profile analysis illustrates that the fluorine ion implantation in the SOI structures modifies the distribution of nitrogen that results in better stoichiometry of the buried silicon nitride layers and abrupt Si3N4–Si interfaces. Current–voltage and high frequency capacitance–voltage characteristics were measured, and electrical breakdown measurements were performed on metal-nitride-silicon (MNS) structures, fabricated after removing the Si overlayer in the SOI structures. In the fluorine-implanted SOI specimens, the buried Si3N4 layers show a higher breakdown field strength of 4.4–5.2 MV/cm as compared to 3.5–4.0 MV/cm in the nonfluorine-implanted one. The capacitance–voltage analysis of the MNS capacitors reveals that the buried Si3N4–Si substrate interface exhibits a better quality with reduced fixed insulator charge and interface state densities after the fluorine ion implantation. Midgap interface state density at the buried Si3N4–Si substrate interface was as low as 1.48×1011 cm−2 eV−1 after the fluorine implantation, which is comparable to that of silicon nitride films deposited on silicon by the conventional low pressure chemical vapor deposition technique. The role of fluorine in improving the basic electrical properties of these SOI structures has been discussed.

Electrical properties of metal–insulator–semiconductor structures with silicon nitride dielectrics deposited by low temperature plasma enhanced chemical vapor deposition distributed electron cyclotron resonance

The present article reports a study of current–voltage (J–E) and capacitance–voltage (C–V) measurements on metal–insulator–semiconductor diodes, using SiNx:H as an insulator layer and Si or InP as semiconductors. We have deposited SiNx:H films by distributed electron cyclotron resonance plasma enhanced chemical vapor deposition at floating temperature, with physical properties similar to films prepared at 800 °C by low pressure chemical vapor deposition. Silane and nitrogen were used as the reactive gases. The experimental results show that the resistivity (ρ) and the critical field (EC) are a strong function of the dielectric composition. For films deposited under optimum conditions, ρ was equal to 1016 Ω cm and EC reached 3.65 or 4.5 MV/cm for Al/SiNx:H/Si and Al/SiNx:H/InP diodes, respectively. The dominant mode of electronic conduction appears to be the Poole–Frenkel emission. The postmetallization annealing (PMA) has no significant effect on these bulk properties (ρ, EC and electronic conduction). On the contrary, PMA has been shown to mainly affect the properties of both SiNx:H/Si and SiNx:H/InP interfaces. The optimized Al/SiNx:H/Si fabrication procedure induced a midgap interface state density (Dit) of 6×1010 eV−1 cm−2 evaluated by high frequency and quasistatic C–V characteristics. In the case of Al/SiNx:H/InP diodes, we have found that the carrier trapping by direct tunneling near the SiNx:H/InP interface is dominant.

Advantages of LDD-only implanted fluorine with submicron CMOS technologies

The effect of fluorine implantation on the properties of shallow n/sup +//p junctions has been investigated. The novel approach of this work lies in the introduction of fluorine only in the LDD regions of the device and not in the active region underneath the gate. Gated diodes were used as test vehicles to study the effect of the fluorine incorporation. Gated diodes are ideal for measurements of this nature since they are sensitive to changes in the interfacial properties near the gate to diffusion overlap region. Results from electrical device characterization indicate a reduction in gated diode leakage and mid-gap interface state density as the F-implanted dose is increased without causing any significant change in the flat-band voltages. Results also showed that samples with F incorporation tended to be more robust to electrical stress than those without F. Materials analysis indicated reduced junction depths for samples with F introduced in the LDD regions indicating suppression of phosphorus dopant diffusion.

Electrical properties of oxides grown on strained Si using microwave N2O plasma

Microwave plasma oxidation (below 200 °C) of strained Si on relaxed Si1−xGex buffer layers in N2O ambient is reported. The electrical properties of grown oxide have been characterized using a metal-oxide-semiconductor structure. Fixed oxide charge density and mid-gap interface state density are found to be 6×1010 cm−2 and 1.2×1011 cm−2 eV−1, respectively. The oxide on strained-Si samples has exhibited hole trapping behavior and moderately low interface state generation on constant current stressing.

Low D/sub it/, thermodynamically stable Ga/sub 2/O/sub 3/-GaAs interfaces: fabrication, characterization, and modeling

Thermodynamically stable, low D/sub it/ amorphous Ga/sub 2/O/sub 3/-(100) GaAs interfaces have been fabricated by extending molecular beam epitaxy (MBE) related techniques. We have investigated both in situ and ex situ Ga/sub 2/O/sub 3/ deposition schemes utilizing molecular beams of gallium oxide. The in situ technique employs Ga/sub 2/O/sub 3/ deposition on freshly grown, atomically ordered (100) GaAs epitaxial films in ultrahigh vacuum (UHV); the ex situ approach is based on thermal desorption of native GaAs oxides in UHV prior to Ga/sub 2/O/sub 3/ deposition. Unique electronic interface properties have been demonstrated for in situ fabricated Ga/sub 2/O/sub 3/-GaAs interfaces including a midgap interface state density D/sub it/ in the low 10/sup 10/ cm/sup -2/ eV/sup -1/ range and an interface recombination velocity S of 4000 cm/s. The existence of strong inversion in both n- and p-type GaAs has been clearly established. We will also discuss the excellent thermodynamic and photochemical interface stability. Ex situ fabricated Ga/sub 2/O/sub 3/-GaAs interfaces are inferior but still of a high quality with S=9000 cm/s and a corresponding D/sub it/ in the upper 10/sup 10/ cm/sup -2/ eV/sup -1/ range. We also developed a new numerical heterostructure model for the evaluation of capacitance-voltage (C-V), conductance-voltage (G-V), and photoluminescence (PL) data. The model involves selfconsistent interface analysis of electrical and optoelectronic measurement data and is tailored to the specifics of GaAs such as band-to-band luminescence and long minority carrier response time /spl tau//sub R/. We will further discuss equivalent circuits in strong inversion considering minority carrier generation using low-intensity light illumination.

Integrated processing of silicon oxynitride films by combined plasma and rapid-thermal processing

Silicon oxynitride (OXN) gate dielectric thin films have been prepared in a cluster tool using a low thermal-budget process combining plasma and rapid-thermal step. This N2-based process has (i) increased process latitude for the formation of N-rich alloys, and (ii) resulted in lower bonded-H concentrations, in comparison to NH3-based processes. On-line Auger electron spectroscopy and off-line infrared spectroscopy have been used to characterize chemical bonding, showing that the deposited films are pseudobinary alloys, (SiO2)x(Si3N4)1−x. The processing steps are (i) a 300 °C plasma-assisted oxidation, (ii) a 300 °C plasma-assisted chemical vapor deposition of oxynitride films, and (iii) a 30 s, 900 °C postdeposition rapid-thermal anneal. Electrical characterization of O–OXN–O structures in metal–oxide–semiconductor capacitors was performed using capacitance–voltage techniques to evaluate the effect of alloy composition on midgap interface state density, Dit, and flat-band voltage, Vfb.

Quasistatic and high frequency capacitance–voltage characterization of Ga2O3–GaAs structures fabricated by in situ molecular beam epitaxy

Interface properties of Ga2O3–GaAs structures fabricated using in situ multiple-chamber molecular beam epitaxy have been investigated. The oxide films were deposited on clean, atomically ordered (100) GaAs surfaces at ≂600 °C by electron-beam evaporation using a Gd3Ga5O12 single-crystal source. Metal–insulator–semiconductor structures have been fabricated in order to characterize the Ga2O3–GaAs interface by capacitance–voltage measurements in quasistatic mode and at frequencies between 100 Hz and 1 MHz. The formation of inversion layers in both n and p-type GaAs has been clearly established. Using the quasistatic/high frequency technique, the interface state density has been derived as a function of band gap energy and a midgap interface state density in the mid 1010 cm−2 eV−1 range has been inferred. Charge trapping in the oxide has been revealed as the dominant trapping mechanism.

Photo-processing of silicon nitride

Silicon nitride films were synthesized using the new process of photo-chemical vapour deposition (photo-CVD). Films of different compositions were prepared by mercury-sensitized photo-CVD using 2% silane and ammonia as reactant gases. Material properties of interest to device technology have been evaluated. Dependence of the properties of the films on the Si/N ratio and the amount of hydrogen present in the films is studied, and optimum growth conditions of deposition are identified. Studies of metal-insulators-semiconductor structures with the optimized photo nitride as an active dielectric showed fixed charge ∼ 1.2 × 10 11 cm −2, mobile charge 3 × 10 10 cm −2 and midgap interface state density ∼ 1.7 × 10 11 eV −1 cm −1 indicating their potential for use in metal-organic-semiconductor technology. A limited comparison of data with direct photo-CVD is also given.

Characterizations of Ultra-thin Dielectrics Grown by Microwave Afterglow O2/N2O Plasma Oxidation at Low Temperature with Rapid Thermal Annealing

AbstractMicrowave afterglow plasma oxidation at a low temperature (600 °C ) and rapid thermal annealing (RTA) were combined to grow high quality ultra-thin dielectrics. This new approach has a low thermal budget. The mid-gap interface state density of oxides pretreated in N2O plasma was decreased to about 5×1010 cm−2eV−1 after rapid thermal annealing at 950 °C.It was found that RTA is very effective for relieving the oxide stress and reducing the interface state density. Nitrogen incorporated in oxides by the N2O plasma pretreatment of the Si surface helped to reduce the interface state density. Microstructures of ultra-thin oxide grown by microwave afterglow oxidation with or without RTA were revealed by extended-X-ray-absorption-finestructure (EXAFS) and X-ray photoelectron spectroscopy (XPS) analysis.

Plasma-grown oxides on silicon with extremely low interface state densities

Plasma-grown oxides on silicon with midgap interface state densities less than 10 10 cm −2 eV −1 have been obtained using low process temperatures (<120°C). Slow and fast interface state densities were measured over a wide frequency range by two different techniques: the quasistatic (CV) and the conductance ( G p /w ) methods. Careful attention to system apparatus design, cleanliness and operation are thought to be the main factors responsible for the low interface trap densities.

Low temperature passivation of Si1−xGex alloys by dry high pressure oxidation

Thermal passivation of Si1−xGex using high pressure (70 MPa) oxidation was studied for potential use in MOS-device applications. Alloys of CVD-grown Si1−xGex (x = 10 and 15 at.%, 200 and 150 nm thick, respectively), were oxidized at 500 and 550°C using high purity dry oxygen at a pressure of 70 MPa. For comparative purposes, a second set of alloys were oxidized using conventional wet atmospheric pressure oxidation at 800°C. X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, transmission electron microscopy (TEM), and metal-oxide semiconductor capacitance-voltage (C-V) measurements were used to characterize the as-grown oxides. Chemical analysis by XPS confirmed that under high pressure conditions compositionally congruent oxides are grown from these alloys. High resolution TEM and Raman spectroscopy show that the as-grown oxide/semiconductor interface is planar and free of Ge enrichment on a scale of 1-2 monolayers. A midgap interface state density for both the 10 and 15 at.% samples of 1 × 1012 cm−2 eV−1 was estimated based on 1 MHz C-V measurement.

Modeling and characterization of interface state parameters and surface recombination velocity at plasma enhanced chemical vapor deposited SiO2–Si interface

The effective surface recombination velocity (Seff) at plasma enhanced chemical vapor deposited (PECVD) SiO2/Si interface as a function of surface band bending under illumination was obtained by combining the photoconductive voltage decay measurements with indium tin oxide gate bias voltage, metal-oxide-semiconductor-capacitance voltage, measurements and theoretical calculations. The capture cross sections for electrons and holes are obtained for the first time for the PECVD SiO2/Si interface state. Theoretical calculations of Seff based on the interface parameters, including interface state density and cross sections for electron and hole, were performed to see the effects of the positive oxide charge density (Qox) on Seff. It is found that roughly a 10 times larger value of Qox compared to the midgap interface state density is required to reduce Seff below 10 cm/s for 5 Ω cm (100) p-type Si. These results prove the potential of PECVD SiO2 for effective passivation of Si surfaces for devices like solar cells.

Effect of synchrotron radiation on electrical characteristics of SiOxNy thin films formed by rapid thermal processing in a N2O ambient

The synchrotron radiation durability of SiOxNy films (about 10 nm) formed by rapid thermal processing in a N2O ambient was studied. No significant difference between the flat-band voltage of SiOxNy-metal-oxide semiconductors (MOS) capacitors patterned by synchrotron radiation lithography (SR-MOS) and that of capacitors patterned by conventional optical lithography (OP-MOS) was observed. The midgap interface state density of the SR-MOS was approximately one order of magnitude larger than that of the OP-MOS. The differences between the SR-MOS and the OP-MOS were nearly independent of the SR dose in the range of 540–2700 mJ/cm2, and were eliminated by annealing in a hydrogen ambient at 400 °C for 30 min.