Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Abstract

Abstract Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n -type Si(100) substrates. Activation of boron-implanted p + polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n -type substrate was investigated by performing a quasi-static C – V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D it , between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p + poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.