Speed Microprocessors Research Articles

Digital Image Evolution of Artwork Without Human Evaluation Using the Example of the Evolving Mona Lisa Problem

Whether for optimizing the speed of microprocessors or for sequence analysis in molecular biology — evolutionary algorithms are used in astoundingly many fields. Also, the art was influenced by evolutionary algorithms — with principles of natural evolution works of art that can be created or imitated, whereby initially generated art is put through an iterated process of selection and modification. This paper covers an application in which given images are emulated evolutionary using a finite number of semi-transparent overlapping polygons, which also became known under the name “Evolution of Mona Lisa”. In this context, different approaches to solve the problem are tested and presented here. In particular, we want to investigate whether Hill Climbing Algorithm in combination with Delaunay Triangulation and Canny Edge Detector that extracts the initial population directly from the original image performs better than the conventional Hill Climbing and Genetic Algorithm, where the initial population is generated randomly.

Electronic-photonic arithmetic logic unit for high-speed computing

The past two decades have witnessed the stagnation of the clock speed of microprocessors followed by the recent faltering of Moore’s law as nanofabrication technology approaches its unavoidable physical limit. Vigorous efforts from various research areas have been made to develop power-efficient and ultrafast computing machines in this post-Moore’s law era. With its unique capacity to integrate complex electro-optic circuits on a single chip, integrated photonics has revolutionized the interconnects and has shown its striking potential in optical computing. Here, we propose an electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits. We experimentally demonstrate its practicality by implementing a 4-bit arithmetic logic unit consisting of 8 high-speed microdisk modulators and operating at 20 GHz. This approach paves the way to future power-saving and high-speed electronic-photonic computing circuits.

Sub-THz/THz Interconnect, Complement to Electrical and Optical Interconnects: Addressing Fundamental Challenges Related to Communication Distances

The big data era has witnessed expansion of information traffic at a 26% compound annual growth rate (CAGR) during one decade, as shown in Figure 1(a) [1], [2]. Rising data rates magnify hierarchically down to shorter communication distances. That is, data rate increases are exchanged from interdata centers to interrack, interboard, interchip, and intrachip scenarios. For almost two decades, microprocessor speeds have been stalled due to unsustainable power consumption [4], resulting in multicore computer architectures. Although the multicore architecture mitigates the data processing power consumption requirement, it demands higher data communication rates from core to core, due to increasingly complex functionalities and systems. Figure 1(b) presents the input?output (I/O) bandwidth and I/O pin number evolution through time [5], [6]. The I/O bandwidth increases by approximately 2 every two years or 10 every five years, while the I/O pin number grows at a much smaller rate, 1.7 every five years, because of process and mechanical constraints. This results in a widening gap between I/O bandwidth requirements and capabilities, notoriously named the interconnect gap, which has been a major and long-standing challenge for more than a decade.

Design of n-Bit Adder without Applying Binary to Quaternary Conversion

Microprocessor has been considered as most important part in ICs manufacturing and making progress since more than 50 years, so increasing microprocessor speed is paid attention in all technologies. ALU is known as the slowest part in microprocessor because of the ripple carry, nowadays microprocessor uses 8-uints as pipeline, each one has 8-bits for implementing 64-bit, working in this form has been captured the microprocessor development and limited its speed for all its computations. Parallel processing and high speed ICs always trying to increase this speed but unfortunately it remains limited. The contemporary solution for increasing microprocessors speed is the Multiple Valued Logic (MVL) technology that will reduce the 8-bits to 4-qbits, this paper proposes a new design of a 2-qbit full adder (FA) as a basic unit to implement MVL ALU (AMLU) that has 8-units as pipeline, each one consists of 4-qbits to implement 32-qbit which is equivalent to 64-bit, without applying binary to quaternary conversion and vice versa. The proposed design increases microprocessors speed up to 1.65 times, but also a little increase of implementation.

Scrutiny of Leakage Currents with Insulating Materials for Transistor Applications

Continuous reducing the size of transistor technology has enabled extraordinary improvements in the switching speed, density, functionality and cost of microprocessors. Integrated Circuit industry is pursuing Moore’s curve down to deep-nanoscale dimensions. Advanced transistor technology now faces many challenges that together result in static power consumption due to leakage currents. In fact, leakage currents are responsible for more than 50% of the total power consumption in nanoscale designs. In deep-nanoscale arena, this percentage will increase further. However, diagnosing of the interface quality and interaction between insulators and semiconductors is significant to reduce the leakage current and achieve the high performance of switching devices in the nanoscale domain. Continuous scaling down has required drastic decreases of the SiO2 dielectric film thickness to achieve ever-higher capacitance densities. Fundamental limits of SiO2 as a dielectric material, imposed by electron tunneling, will be reached as this SiO2 film thickness approaches ~1nm. Therefore, alternate high-k interlayer dielectric material will be needed to replace SiO2 as a capacitor and gate dielectric material. Numerous alternate high-k materials are being actively investigated, ranging from Al2O3 (k ~ 9) to HfO2 (k ~ 25). High-k materials hold the promise of achieving very high capacitance densities with relatively thick films.

Are technology improvement rates of knowledge industries following Moore's law? An empirical study of microprocessor, mobile cellular, and genome sequencing technologies

Critical technologies in knowledge economy may advance at an exponential rate of improvement. The best known example of such exponential trend of improvement has been provided by Moore's law. First, this paper shows that Moore's law is still valid by examining the development of microprocessor technology for the period from 1971 to 2010. Second, this paper finds that such exponential rate of improvement can be found in other technologies such as mobile cellular and genome sequencing technologies. However, their exponential improvement rates vary from technology to technology. Lastly, this paper examines whether the improvement rate has been slowed down in recent years. This paper finds that the improvement rate has been slowed down in the clock speed of microprocessors. However, there is no such downward trend in transistor density, million instructions per second and mobile cellular technology. On the other hand, the improvement rate became higher over the last ten years in genome sequencing technology which is in the early stages of development.

Are technology improvement rates of knowledge industries following Moore's law? An empirical study of microprocessor, mobile cellular, and genome sequencing technologies

Critical technologies in knowledge economy may advance at an exponential rate of improvement. The best known example of such exponential trend of improvement has been provided by Moore's law. First, this paper shows that Moore's law is still valid by examining the development of microprocessor technology for the period from 1971 to 2010. Second, this paper finds that such exponential rate of improvement can be found in other technologies such as mobile cellular and genome sequencing technologies. However, their exponential improvement rates vary from technology to technology. Lastly, this paper examines whether the improvement rate has been slowed down in recent years. This paper finds that the improvement rate has been slowed down in the clock speed of microprocessors. However, there is no such downward trend in transistor density, million instructions per second and mobile cellular technology. On the other hand, the improvement rate became higher over the last ten years in genome sequencing technology which is in the early stages of development.

Improving Operational Intensity in Data Bound Markov Chain Monte Carlo

Typically, parallel algorithms are developed to leverage the processing power of multiple processors simultaneously speeding up overall execution. At the same time, discrepancy between DRAM bandwidth and microprocessor speed hinders reaching peak performance. This paper explores how operational intensity improves by performing useful computation during otherwise stalled cycles. While the proposed methodology is applicable to a wide variety of parallel algorithms, and at different scales, the concepts are demonstrated in the machine learning context. Performance improvements are shown for Bayesian logistic regression with a Markov chain Monte Carlo sampler, either with multiple chains or with multiple proposals, on a dense data set two orders of magnitude larger than the last level cache on contemporary systems.

PARS: A scheduling of periodically active rank to optimize power efficiency for main memory

The growing gap between microprocessor speed and DRAM speed is a major problem that computer designers are facing. In order to narrow the gap, main memory is expected to grow significantly in both speed and capacity for it is a major shared resource among cores in a multi-core system, which will lead to increasing power consumption, perhaps replacing the dominant consuming fraction of processor. Therefore, it is critical to address the power issue without seriously decreasing performance in the main memory subsystem. In this paper, we propose a periodically active rank scheduling (PARS) to optimize power efficiency for DRAM in smart phones. Our scheduling features a three-step design. First, we partition all threads in the system into groups. Second, we modify page allocation policy to achieve threads in the same group which occupies the same rank but different banks of DRAM. Finally, we sequentially schedule threads in one group after another while only active running group׳s ranks to retain other ranks low power status. As a result, our scheduling periodically activates one rank after another to optimize memory power efficiency. We implement PARS in Linux 2.6.39 kernel running randomly generated workloads containing single-threaded and multi-threaded benchmark. Experimental results show that PARS can improve both the memory power efficiency by 26.8% and performance by 4.2% average relative to default system while reducing negligible fairness.

Communication Capital, Metcalfe's Law, and U.S. Productivity Growth

This paper analyzes the contribution of network externalities to the pickup in U.S. productivity in the early 2000s. The Internet and wireless communication are treated as the central mechanisms of ICT-driven productivity growth. The approach contrasts with the dominant view in the macro-productivity literature, which places microprocessor speed and computational capacity at center stage (e.g., Jorgenson 2001). The usual sources-of-growth model is adapted for network effects and network utilization, and new metrics for communication capital and its productivity are introduced. The adapted model and metrics significantly aid understanding how the spread of high-speed networking and wireless communications (via Metcalfe’s Law and ICT as a GPT, or “network effects” for short) have profoundly shaped the modern productivity performance of the United States. Under exceedingly modest assumptions, the model and metrics developed in this paper suggest network effects contributed nearly 0.5 percentage points to productivity growth annually from 2000 to 2007, or 32 percent of the overall change in MFP.

Continuous prediction of manufacturing performance throughout the production lifecycle

We describe methods for continual prediction of manufactured product quality prior to final testing. In our most expansive modeling approach, an estimated final characteristic of a product is updated after each manufacturing operation. Our initial application is for the manufacture of microprocessors, and we predict final microprocessor speed. Using these predictions, early corrective manufacturing actions may be taken to increase the speed of expected slow wafers (a collection of microprocessors) or reduce the speed of fast wafers. Such predictions may also be used to initiate corrective supply chain management actions. Developing statistical learning models for this task has many complicating factors: (a) a temporally unstable population (b) missing data that is a result of sparsely sampled measurements and (c) relatively few available measurements prior to corrective action opportunities. In a real manufacturing pilot application, our automated models selected 125 fast wafers in real-time. As predicted, those wafers were significantly faster than average. During manufacture, downstream corrective processing restored 25 nominally unacceptable wafers to normal operation.

A 10-T SRAM Cell with Inbuilt Charge Sharing for Dynamic Power Reduction

As microprocessors and other electronics applications get faster and faster, the need for large quantities of data at very high speeds increases, while providing the data at such high speeds gets more difficult to accomplish. As microprocessor speeds increase from 25 MHz to 100 MHz, to 250 MHz and beyond, systems designers have become more creative in their use of cache memory, interleaving, burst mode and other high-speed methods for accessing memory. Speed The primary advantage of an SRAM over a DRAM is its speed. A novel 10-T SRAM cell design with an inbuilt mechanism for charge recycling to cut down the dynamic power budget. The read discharge power of a single ended 8T cell is reused efficiently in the proposed cell architecture. The proposed design is built after analyzing the different types of SRAM using low power design techniques.

An Expert System for Full pH Range Prediction Using a Disposable Optical Sensor Array

The design of optical sensor arrays encompasses tasks such as the acquisition of sensor optical parameters, as for example color features, and the calibration of a multivariate method to model the array global behavior. Different techniques have been used to model the sensor array responses, such as multivariate regression or neural networks, although they show certain limitations. The former methods require either high amount of computer memory or speed so therefore they are not suitable for implementation in portable electronic devices with low resources, while the later is a black box whose operation cannot be easily modeled and explained for industrial development validation. This work addresses these problems and proposes an expert system to overcome the previous drawbacks. The approach makes an accurate pH prediction, and it comprises a balance between memory and microprocessor speed for its integration within embedded systems with low memory and chip resources. In addition, it is also able to provide a high expressive explanation of why such prediction was made, so that the industrial validation is easier than using other proposals such as neural networks.

Memory access schedule minimization for embedded systems

The growing gap between microprocessor speed and DRAM speed is a major problem that computer designers are facing. In order to narrow the gap, it is necessary to improve DRAM's speed and throughput. To achieve this goal, this paper proposes techniques to take advantage of the characteristics of the 3-stage access of contemporary DRAM chips by grouping the accesses of the same row together and interleaving the execution of memory accesses from different banks. A family of Bubble Filling Scheduling (BFS) algorithms are proposed in this paper to minimize memory access schedule length and improve memory access time for embedded systems. When the memory access trace is known in some application-specific embedded systems, this information can be fully utilized to generate efficient memory access schedules. The offline BFS algorithm can generate schedules which are 47.49% shorter than in-order scheduling and 8.51% shorter than existing burst scheduling on average. When memory accesses are received by the single memory controller in real time, the memory accesses have to be scheduled as they come. The online BFS algorithm in this paper serves this purpose and generates schedules which are 58.47% shorter than in-order scheduling and 4.73% shorter than burst scheduling on average. To improve the memory throughput and further reduce the memory access schedule, an architecture with dual memory controllers is proposed. According to the experimental results, the dual controller algorithm can generate schedules which are 62.89% shorter than in-order scheduling, 14.23% shorter than burst scheduling, and 10.07% shorter than single controller BFS algorithms on average.

Emerging Technologies in Implantable Auditory Prostheses

Program Description: Current prosthetic auditory implants have achieved a high level of success, however, it would be fair to say that performance gains over the past decade have reached a stable plateau. The latest phase of development has centered primarily on increasing stimulus resolution, preserving residual auditory ultrastructure and function, and implanting higher order neural pathways. To serve these objectives, electrodes have been designed to more closely approximate the spiral ganglion and be inserted virtually atraumatically. Implantation of the higher order pathways has already been performed with combinations of penetrating needles or electrode paddles at the brainstem. Prototypes even exist for stimulation as high up as the auditory cortex. We are now also witnessing the development of highly focused fiberoptic delivery systems for infrared laser energy as the stimulus source. A panel of surgeons and scientists, all of whom have been involved in both clinical and basic science of auditory implants, will debate the strategies being developed to foster the next leap in performance gains. The seminar will begin with a candid appraisal of the successes of currently marketed achievements including modiolar hugging electrodes, hearing preservation hybrid implants, compressed and split arrays for severely malformed and obstructed cochleae, and bilateral implantation. Minimally invasive surgical techniques will be examined with the questions posed: What truly constitutes a minimally invasive procedure? What technical features need to be retained in order to maintain necessary safeguards and precautions? The variable successes of auditory brainstem implantation will be reviewed with an eye toward future improvement. The panelists will then present their collective experience with emerging technologies aiming to push the envelope of performance higher into the future. The constant gains in microprocessor speeds will offer opportunities for development of novel processing strategies including current steering. The emerging concept of integrated drug delivery systems will require a careful re-exploration of the well-known design problems of hermeticity, durability, and ultrastructural trauma induction. Changes in stimulus energy source (eg, infrared laser) will undoubtedly require radical changes in device designs and coding strategies. It is the hope of the organizers that this miniseminar will benefit both the attendees and the panelists through the process of evaluative debate and exploration of new ideas. Educational Objectives: 1) Understand the current status and future direction of hybrid “hearing preservation” cochlear implantation. 2) Understand the newest device and coding strategies including infrared laser optical based devices. 3) Be familiar with the current systems under development including vestibular prostheses, DACS and ABI.

The Changing Patient in the Digital Era: A Typology for Guiding Innovation in Healthcare

Ten years ago, the word blog would have drawn puzzled stares. The iPhone was inconceivable. The inventor of Facebook was 15. To understand the impact of the explosion of and social media technologies on healthcare, it is important to understand how these technologies are changing the consumers who use them. Today’s unrelenting technological progress is providing consumers countless new ways of receiving and distributing information and content that was not available years or even months ago. Consumers’ increasing use of media to learn, interact, and connect with others on demand is changing their expectations for access to information and connection in all areas of their lives – including healthcare. As consumers change their expectations, new businesses are emerging to meet their every wish, even every potential wish. Healthcare is no exception. Patients, families and caregivers, and individuals interested in wellness find themselves in a marketplace that is changing by the month. They have access to a wealth of new information sources, new services, new ways of connecting with each other, and new apps (applications) across multiple devices — all designed to put them in charge of their own healthcare. At times medical professionals can experience their digitally-savvy patients as irritating. Most healthcare providers are familiar with patients who arrive at medical visits with a potential diagnosis derived from a website that has little to do with an accurate assessment of their condition. However, as websites offer increasingly sophisticated interactive assessments and tools, often sponsored by medical associations (The American Heart Association, The American Cancer Society) or developed by physicians, patients are entering with better questions, with a clearer perspective on their health challenges. These patients may have an enhanced understanding of the actions required from themselves as well as from their doctors. Patients’ digital life can become a useful adjunct to their in-person visits with medical staff in a healthcare facility In addition, as more and more patients are being seen for long-term, chronic conditions that are strongly influenced by their lifestyle choices outside of medical treatment, the world can serve as a useful partner in care. The choices patients and their families make when they are at home, at work, or in other locations, may affect their health as much as the treatment choices made in the medical office or hospital. For those with Internet access, the world is always there for them. Patients can take advantage of monitoring devices, sensors, useful information, or support around the clock, from any location. What we are witnessing is nothing short of revolutionary, not just in terms of technological advances, but also in terms of the shifting attitudes, expectations, behaviors, and culture. Digital Media as the Driver of Exponential Change in Healthcare The recent wave of new technology is strongly influenced by the exponential growth of microprocessor speed. Intel co-founder Gordon Moore hypothesized that processing speed of integrated circuits would double in speed every two years, while halving in cost and size. This relentless year-after-year development has led to unprecedented product turnover in very short periods of time. A product or service that is dominant today can be obsolete within a year or less. Exponential change is often hard for humans to understand. Many innovations have changed humanity profoundly throughout our history — agriculture, the printing press, the internal combustion engine — but none of these discoveries were based on microprocessors. They did not double in speed every two years. A page from Intel’s website urges readers to consider, “In 1978, a commercial flight between New York and Paris cost around $900 and took seven hours. If the principles of Moore’s Law had been applied to the airline industry the way they have to the semiconductor industry since 1978. that flight would now cost about a penny and take less than one second.” 1

A five-year hedonic price breakdown for desktop personal computer attributes in Brazil

The purpose of this article is to identify the attributes that discriminate the prices of personal desktop computers. We employ the hedonic price method in evaluating such characteristics. This approach allows market prices to be expressed as a function, a set of attributes present in the products and services offered. Prices and characteristics of up to 3,779 desktop personal computers offered in the IT pages of one of the main Brazilian newspapers were collected from January 2003 to December 2007. Several specifications for the hedonic (multivariate) linear regression were tested. In this particular study, the main attributes were found to be hard drive capacity, screen technology, main board brand, random memory size, microprocessor brand, video board memory, digital video and compact disk recording devices, screen size and microprocessor speed. These results highlight the novel contribution of this study: the manner and means in which hedonic price indexes may be estimated in Brazil.

High-Performance Computing Applications on Novel Architectures

As chip designers struggle to increase the speed of conventional microprocessors, the scientific computing community is turning its attention to alternative architectures that utilize computational accelerators to improve the application performance. This special issue of CiSE examines several examples of computationally demanding applications implemented on novel high-performance computing architectures and points out the challenges and opportunities that these new architectures bring up.

Analysis of String Matching Compression Algorithms

The improvement rate in microprocessor speed by far exceeds the improvement in DRAM memory. This increasing processor-memory performance gap is the primary obstacle to improved computer system performance. As a result, the size of main memory has increased gradually. To utilize main memory’s resources effectively, data compression can be applied. Through compression, the data can be compressed by eliminating redundant elements. Thus, this study incorporates compression to main memory in order to fully utilize its resources and improve performance of data access. This project evaluates the performance of the compression algorithms in order to increase the performance of memory access. The compression algorithms are string matching based which are LZW and LZSS. Through simulation, the effectiveness and compressibility of the algorithms were compared. The performances of the algorithms were evaluated in term of compression time, decompression time and compressed size. The simulation result shows that LZSS is an efficient compression algorithm compared to LZW.

Improving memory system performance with energy-efficient value speculation

Microprocessor speeds have been improving much faster than memory speeds, resulting in the CPU spending a larger and larger amount of time waiting for data. Processor designers have employed several ways to improve memory performance, including hierarchical caching, prefetching, and faster memory chips. Yet, memory accesses still represent a major performance bottleneck and much remains to be done to tolerate the increasing memory latencies. Load-value prediction has been shown to effectively hide some of this latency. However, the hardware required to achieve good performance is substantial, making load-value prediction unappealing in light of increasing power constraints. In this paper, we present a novel predictor that significantly increases CPU performance while at the same time decreasing the energy consumption of the entire processor relative to a baseline with a well-performing hybrid load-value predictor.