A 10-T SRAM Cell with Inbuilt Charge Sharing for Dynamic Power Reduction

Abstract

As microprocessors and other electronics applications get faster and faster, the need for large quantities of data at very high speeds increases, while providing the data at such high speeds gets more difficult to accomplish. As microprocessor speeds increase from 25 MHz to 100 MHz, to 250 MHz and beyond, systems designers have become more creative in their use of cache memory, interleaving, burst mode and other high-speed methods for accessing memory. Speed The primary advantage of an SRAM over a DRAM is its speed. A novel 10-T SRAM cell design with an inbuilt mechanism for charge recycling to cut down the dynamic power budget. The read discharge power of a single ended 8T cell is reused efficiently in the proposed cell architecture. The proposed design is built after analyzing the different types of SRAM using low power design techniques.