Abstract
The big data era has witnessed expansion of information traffic at a 26% compound annual growth rate (CAGR) during one decade, as shown in Figure 1(a) [1], [2]. Rising data rates magnify hierarchically down to shorter communication distances. That is, data rate increases are exchanged from interdata centers to interrack, interboard, interchip, and intrachip scenarios. For almost two decades, microprocessor speeds have been stalled due to unsustainable power consumption [4], resulting in multicore computer architectures. Although the multicore architecture mitigates the data processing power consumption requirement, it demands higher data communication rates from core to core, due to increasingly complex functionalities and systems. Figure 1(b) presents the input?output (I/O) bandwidth and I/O pin number evolution through time [5], [6]. The I/O bandwidth increases by approximately 2 every two years or 10 every five years, while the I/O pin number grows at a much smaller rate, 1.7 every five years, because of process and mechanical constraints. This results in a widening gap between I/O bandwidth requirements and capabilities, notoriously named the interconnect gap, which has been a major and long-standing challenge for more than a decade.
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