Abstract

Microprocessor has been considered as most important part in ICs manufacturing and making progress since more than 50 years, so increasing microprocessor speed is paid attention in all technologies. ALU is known as the slowest part in microprocessor because of the ripple carry, nowadays microprocessor uses 8-uints as pipeline, each one has 8-bits for implementing 64-bit, working in this form has been captured the microprocessor development and limited its speed for all its computations. Parallel processing and high speed ICs always trying to increase this speed but unfortunately it remains limited. The contemporary solution for increasing microprocessors speed is the Multiple Valued Logic (MVL) technology that will reduce the 8-bits to 4-qbits, this paper proposes a new design of a 2-qbit full adder (FA) as a basic unit to implement MVL ALU (AMLU) that has 8-units as pipeline, each one consists of 4-qbits to implement 32-qbit which is equivalent to 64-bit, without applying binary to quaternary conversion and vice versa. The proposed design increases microprocessors speed up to 1.65 times, but also a little increase of implementation.

Highlights

  • MICROPROCESSOR is considered as the core of diverse systems like PC and embedded systems

  • Adder is known as the main and basic part of processing element, so that, optimization of the adder circuit will lead to an improvement of the processing unit. This optimization will effect on calculation time of Arithmetic Logic Unit (ALU), and the performance of the unit will be improved [1]

  • Because of the constraints of parallel processing, new technologies still have some limitations that prevent it from improving the performance of microprocessor, but these limitations did not stop researchers to find some enhancements in this field

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Summary

Introduction

MICROPROCESSOR is considered as the core of diverse systems like PC and embedded systems. It is a new theory proposed by Zaghar for satisfying the important requirements of multiple valued logic in quaternary [9, 10]. It consists of three major phases which will be explained as follows

Phase One
Phase Two
Phase Three
System Evaluation
Conclusion
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