Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

Abstract

The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).