Abstract
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed on Cadence Design Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm technology with a unvaried width and length of PMOS and NMOS devices. The paper gives a compression of various design of 1 bit full adder with respect to number of transistors/ gate count, Delay, Power and Power Delay Product.
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