Design and Simulation of High Performance Hybrid Full Adder Using CMOS 45 nm Technology

Abstract

AbstractThe new blended model is mostly utilized in the designing process of an arithmetic circuitry. The efficiency of a full adder with the factors of holding time, potential charge utility and the strength of the circuit is highly based on how efficiently the circuit will work. From this project, a large speed, low power consuming count of ten transistors logic circuit is designed, and it generates effective fluctuations at the same time with effective delay at output. The performance efficiency of the designed circuit is calculated by simulating it in a tanner software using 45 nm technology. The established circuit decreases the PDP factor at least by 15% than already existing XOR–XNOR models. In this project we are introducing two different designs of full adders those are designed in this article by using the already designed XOR–XNOR circuitry and existed sum and carry generating blocks. The designed full adders provides 10–40% betterment in words of power fluctuation product in the comparison of other models. To calculating the driving capacities the proposed full adders are fixed in multistage full adder circuits. Outputs show that two of the designed full adders generate the better results for a larger count of data bits in all the full adders.KeywordsMultistage adderHigh fluctuationBlended full adderLogic circuit