Metal Oxide Semiconductor Transistors Research Articles

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

Embedded dynamic random-access memories (eDRAM) are widely used in the design of embedded systems for the safeguard of information during their operation. However, since these memories are installed in the same chip as the host system, it is crucial to consider their dimensioning. For this reason, in our work, the aspect ratio width and length (W/L) of complementary metal oxide semiconductor (CMOS) transistors inside 3-transistor logic cells (3T) is diversified to evaluate the effect on electrical behavior with area optimization through the figure of merit (FoM): power consumption-delay product of 8-bit memories with an operating frequency of 8.3 MHz, varying the aspect ratio of transistors inside the cell have been obtained 8.6f as lowest and 152.3f as highest FoM values. Those storage devices have been developed on 0.00085 mm2 using a 180-nm CMOS technology.

Power-Efficient Electronically Tunable Fractional-Order Filter

This article describes a low-voltage, low-power fractional-order low-pass filter (FO-LPF) of order 1 + α, which is implemented using a voltage differencing differential difference amplifier (VDDDA). The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor transistor technique. The transistors operate in the subthreshold region to maintain low-supply voltage and low-power consumption. The FO-LPF structure implemented using this VDDDA structure is compact. It includes three VDDDAs and three grounded capacitors along with two active resistors implemented using MOS transistors. In addition, this filter structure provides electronic tuning of its order and cut-off frequency through the bias current of the active component used. The effects of tracking error and parasitics on the functionality of the proposed FO-LPF were investigated. The VDDDA and filter operate at ±300 mV and dissipate only 207 nW and 663 nW of power, respectively. Thus, the VDDDA structure and filter are suitable for low-voltage and low-power operation. Layouts of the proposed VDDDA as well as the FO-LPF were designed in the Cadence Virtuoso environment. Post-layout simulation results of the designed circuits imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo, and PVT analyses were also performed.

Separate evaluation of interface and oxide hole traps in SiO2/GaN MOS structures with below- and above-gap light excitation

Understanding the traps in metal-oxide-semiconductor (MOS) structures is crucial in the fabrication of MOS transistors with high performance and reliability. In this study, we evaluated the hole traps in SiO2/GaN MOS structures through photo-assisted capacitance-voltage measurements. Below- and above-gap light was used to distinguish between the contributions of fast interface and slow oxide hole traps. While annealing in oxygen is effective in reducing the oxide hole traps, a high density of hole traps exceeding 1012 cm−2eV−1 remains at the interface. Although these traps are donor-type and thus hidden in n-type MOS structures, they could impair the switching performance of GaN MOS transistors.

Development of seven MOS transistors, one capacitor based efficient and compact novel structure of phase-shifter

In this paper, a novel electronically tunable first-order voltage-mode phase-shifter is introduced, which employs seven metal-oxide semiconductor transistors and one capacitor. The attractive features of the proposed electronically tunable first-order voltage-mode phase-shifter are the low number of metal-oxide semiconductor transistors, free from additional current sources, electronic tunable, free from passive component matching conditions, high input impedance, low operating voltage, and availability of both inverting all-pass and non-inverting all-pass responses within the same structure. The theoretical analysis of the proposed circuit is tested by Cadence PSPICE Simulation software with ±0.9 V supply voltages. Pre- and post-layout verification are also explored using the Cadence VIRTUOSO simulation tool and 0.18 µm Generic Process Design Kit (gpdk) technology to confirm the real-time performance of the proposed design.

VLSI Implementation of Hybrid Memristor Based Logic Gates

Practical memristors have gained attention from researchers and scientists due to their potential use in a variety of electronic circuits and devices. In our paper, a hybrid Memristor-CMOS (MeMOS) logic circuit was designed and its transient response was analyzed. This circuit, which uses a N-type metal oxide semiconductor (NMOS), and P-type metal oxide semiconductor (PMOS) transistors, Operational amplifiers (OPAMPs), resistors, capacitors and multipliers replicate memristor characteristics. To facilitate the development of real memristor circuit applications, a memristor emulator is utilized for breadboard experiments. This emulator can be connected in a variety of configurations, including serial, parallel, or a combination of both, with identical or opposite polarities. By simply changing the connection, the emulator can be switched between decremental and incremental configurations. In our paper, we implemented AND logic using MeMOS. PSpice simulation of the proposed emulator have been demonstrated for TiO2 memristor model.

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical character-istics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

CMOS-Compatible Titanium-Based Micro Supercapacitor With Outstanding Capacitance and Frequency Performances

Micro supercapacitors (MSCs) with high capacitance density offer enormous potential for on-chip energy storage and power supply filtering. However, the capacitance decay under an AC condition and incompatibility with Complementary Metal Oxide Semiconductor Transistor (CMOS) processes greatly restrict their application as filtering capacitors in integrated circuits. This work presents a wafer-level MSC with outstanding capacitance and frequency performances, contributed by the hybrid TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti electrode structure and a novel CMOS-compatible fabrication methodology. The highly conductive Ti framework with optimal porous structure provides a fast transfer channel for electrons/ions, while a 6 nm-thick TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , in situ oxidized-grown on the Ti framework, offers exceptional pseudocapacitance. Meanwhile, a 3D electrode architecture is fabricated through a proposed High-Aspect-Ratio Porous Electrode Lift-off (HPEL) process, benefiting capacitance and rate performance. Hence, the MSC shows a capacitance density of 10.12 mF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a high scan rate of 1 V/s with a characteristic frequency of 550 Hz, which is superior to the reported on-chip MSCs. Furthermore, such proposed design and fabrication strategies are simple, low-cost, and CMOS-compatible, promising for mass production.

LPT and SLPT Measurement Methods of Flat-Band Voltage (VFB) in MOS Devices

The photoelectric techniques are often used for the measurements of metal oxide semiconductor (MOS) structure parameters. These methods, which consist in illuminating the MOS structure with a semitransparent metal gate by a UV light beam, are often competitive for typical electric measurements. The results obtained by different photoelectric methods are, in many cases, more accurate and reproducible than the results of other measurements. The flat-band voltage VFB is an important parameter of any MOS structure since its value influences the threshold voltage VT , which decides for example about power consumption of MOS transistors. One of the methods to measure the VFB value is the electric method of C(V) characteristic. This method involves certain calculations and requires the knowledge about parameters of the investigated sample. The accuracy of this method is rarely better than ±100 mV (for higher doping of the substrates the accuracy is worse). The other method of VFB value determination, outlined in this article, is the photoelectric light pulse technique (LPT) method. This method based on the idea proposed by Yun is currently being optimized and verified experimentally.

3D to 2D perspectives - Traditional and new doping and metrology challenges at the nanoscale

In this perspectives paper we will explore the doping state-of-the-art as it evolves for 3D to 2D structures and materials, and the following impact on the metrology methods needed to characterise them. Historically, silicon devices for logic complementary metal-oxide-semiconductor (MOS) are built in bulk monocrystalline substrates. In this context bulk silicon substrates are 3D, as there is not the electrostatic confinement associated with more technologically advanced device structures. The determination of technology figures-of-merit such as sheet resistance, impurity concentration and activation profiles versus depth, and reverse bias leakage current to track crystal quality post-doping process, have been the typical methods for evaluation. Since the emergence of FinFET, gate-all-around (GAA) for logic, and layered 2D materials such as transition-metal-dichalcogenides (TMDs) for MOS channel active areas, these figures-of-merit are more awkward to extract, or simply do not apply in the usual sense. Logic devices, like MOS transistors, depend on doping processes to lower access resistance and thus drive performance, traditionally relied on ion implantation to introduce impurities to the substrate, which is a physical bombardment that damages the target material. Gentler doping processes that rely on in-diffusion are an emerging category, and most recently the concept of terminating or functionalising the (near-) surface of the semiconductor is growing in popularity, at least in research labs. Likewise, methods to characterise these require evolution to adapt to the times, from the conventional high-throughput techniques to the more exploratory, albeit lower throughput, methods. Metrology relies upon high-sensitivity, large dynamic range of detection, spatial resolution, as well as time- and cost-efficient sample preparation and post-analysis data interpretation. Driven primarily by the continued development of novel, scaled-down, truly unique device architectures and the introduction of novel materials in the nano-fabrication technology, the portfolio of dopant characterisation methods is unremittingly enlarging its numbers. Herein, we focus our discussion onto dopant profiling for fin and nanowire FETs, and relate these to analysis of test vehicles such as arrays of fin structures with varying dimensions. Although reports detailing correlative use of the dopant characterisation methods are only a few, we present examples that provided unique new information, in absence of which the overall description of the dopant process is inconclusive and, in some cases, misleading.

A novel PMOS transistors based first-order all-pass network

In this paper, a new voltage-mode first-order all-pass network is introduced. It is realized by using only four p-channel metal–oxide–semiconductor transistors, one resistor and one capacitor. The proposed filter enjoys the feature of high input impedance and does not require any additional current source. It is also free from any kind of passive element matching constraint. In order to test the workability of the proposed structure, a second-order all-pass network and quadrature oscillator are presented. Personal simulation program with integrated circuit emphasis using 0.18 µm, level-7 complementary metal-oxide-semiconductor process parameters with ± 0.9 V supply voltages are used to validate the performance of the proposed structure.

Interface traps, correlated mobility fluctuations, and low-frequency noise in metal–oxide–semiconductor transistors

Interface traps generally are not considered to be likely sources of low-frequency (LF) noise and/or random telegraph noise (RTN) in metal–oxide–semiconductor (MOS) devices because the longer carrier exchange times of border traps are more consistent with experimental observations. In contrast, correlated mobility fluctuations due to remote Coulomb scattering from charged border traps cannot explain the unexpectedly large LF noise and/or RTN observed in some MOS devices. In this Letter it is proposed that equilibrium fluctuations in interface-trap concentrations caused by hydrogen-induced activation and passivation reactions can lead to enhanced LF noise and RTN. This mechanism adds to other noise sources, including border traps, random dopants, and bulk-Si defect clusters.

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

Robust Chaos With Novel 4-Transistor Maps

This brief presents four discrete-time chaotic map circuits, including three new map circuits and one that has been previously reported. The designs are hardware efficient as they each contain only four Metal Oxide Semiconductor (MOS) transistors. They offer robust chaotic performance with wide chaotic space and uniform entropic properties. The wide chaotic region is essential for applications where parametric perturbation can push the system out of the desirable chaotic region. The chaotic performance is analyzed using a bifurcation plot, Lyapunov exponent, correlation coefficient, sample entropy, and Shannon entropy, and improvement over previous transistor-level designs is demonstrated. The proposed method can be useful in applications such as random number generation, reconfigurable and flexible computing, side-channel attack mitigation, logic obfuscation, and chaos-based cryptography. A chaotic oscillator design is proposed and its application in a chaos-based reconfigurable logic gate is presented, as well.

High-k and high-temperature-resistant polysilsesquioxane: Potential for solution-processed metal oxide semiconductor transistors operating at low voltage

High-k and high-temperature-resistant polysilsesquioxane: Potential for solution-processed metal oxide semiconductor transistors operating at low voltage

Band-to-band tunneling switches based on two-dimensional van der Waals heterojunctions

Quantum mechanical band-to-band tunneling is a type of carrier injection mechanism that is responsible for the electronic transport in devices like tunnel field effect transistors (TFETs), which hold great promise in reducing the subthreshold swing below the Boltzmann limit. This allows scaling down the operating voltage and the off-state leakage current at the same time, and thus reducing the power consumption of metal oxide semiconductor transistors. Conventional group IV or compound semiconductor materials suffer from interface and bulk traps, which hinder the device performance because of the increased trap-induced parasitics. Alternatives like two-dimensional materials (2DMs) are beneficial for realizing such devices due to their ultra-thin body and atomically sharp interfaces with van der Waals interactions, which significantly reduce the trap density, compared to their bulk counterparts, and hold the promise to finally achieve the desired low-voltage operation. In this review, we summarize the recent progress on such devices, with a major focus on heterojunctions made of different 2DMs. We review different types of emerging device concepts, architectures, and the tunneling mechanisms involved by analytically studying various simulations and experimental devices. We present our detailed perspective on the current developments, major roadblocks, and key strategies for further improvements of the TFET technology based on 2D heterojunctions to match industry requirements. The main goal of this paper is to introduce the reader to the concept of tunneling especially in van der Waals devices and provide an overview of the recent progress and challenges in the field.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.