Abstract
Micro supercapacitors (MSCs) with high capacitance density offer enormous potential for on-chip energy storage and power supply filtering. However, the capacitance decay under an AC condition and incompatibility with Complementary Metal Oxide Semiconductor Transistor (CMOS) processes greatly restrict their application as filtering capacitors in integrated circuits. This work presents a wafer-level MSC with outstanding capacitance and frequency performances, contributed by the hybrid TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti electrode structure and a novel CMOS-compatible fabrication methodology. The highly conductive Ti framework with optimal porous structure provides a fast transfer channel for electrons/ions, while a 6 nm-thick TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , in situ oxidized-grown on the Ti framework, offers exceptional pseudocapacitance. Meanwhile, a 3D electrode architecture is fabricated through a proposed High-Aspect-Ratio Porous Electrode Lift-off (HPEL) process, benefiting capacitance and rate performance. Hence, the MSC shows a capacitance density of 10.12 mF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a high scan rate of 1 V/s with a characteristic frequency of 550 Hz, which is superior to the reported on-chip MSCs. Furthermore, such proposed design and fabrication strategies are simple, low-cost, and CMOS-compatible, promising for mass production.
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