Metal-oxide-semiconductor Interface Research Articles

Transport Properties in GaN Metal–Oxide–Semiconductor Field‐Effect Transistor Almost Free of Interface Traps with AlSiO/AlN/p‐Type GaN Gate Stack

The factors limiting channel mobility in AlSiO/p‐type GaN metal–oxide–semiconductor (MOS) field‐effect transistors are examined by performing Hall‐effect measurements in conjunction with a gate bias, with and without a thin AlN interlayer. In the absence of this interlayer, the free carrier concentration associated with the Hall effect is significantly reduced compared with the net gate charge density estimated from capacitance–voltage data, indicating that electrons are trapped to a significant extent at the MOS interface. These interface traps are found to have an energy ≈20 meV above the Fermi level in strong inversion based on temperature‐dependent Hall effect data. The insertion of a 0.8 nm‐thick AlN interlayer eliminates charge trapping such that almost all gate charges are mobile. The mobility components could be divided into types based on their effect on the effective electric field perpendicular to the channel. Coulomb scattering centers resulting from interface states are evidently reduced by inserting the AlN interlayer, which also enhances the channel mobility to over 150 cm2 V−1s−1.

Characterization of nitrided SiC(1 [formula omitted] 00) MOS structures by means of electrical measurements and X-ray photoelectron spectroscopy

Interface nitridation in nitric oxide is a standard technique for improving the performance of silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this study, we focused on m-face SiC MOS structures and investigated the impact of nitridation by means of electrical measurements and X-ray photoelectron spectroscopy (XPS). Gate leakage characteristics were measured in a wide temperature range of about −150 – 100 °C, which clarified that nitridation leads to an unwanted increase in the Fowler-Nordheim leakage current. Scanning XPS measurements revealed that the amount of nitrogen incorporated at the m-face MOS interface could reach about 2.3 times higher than the Si-face MOS interface. The incorporation of nitrogen likely reduces the conduction band offset at the SiO2/SiC interface, thereby increasing the gate leakage. This conclusion was further corroborated in an analysis of band alignment based on synchrotron radiation XPS measurements. Therefore, while nitrided m-face SiC MOS devices exhibit superior on-state performances, they have a limitation in terms of reliability.

Simplified Bilayer TFETS with Oxide And Group-IV Semiconductor For P-Channel Operation

The paper proposes a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing for both n- and p-channel TFET operations under the same device structure. The p-IV side in the heterostructure has a metal-oxide-semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current during p-TFET operation. Technology computer-aided design (TCAD) simulation is used to predict the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. The p-TFET operation of the n-ZnSnO/p-SiGe bilayer device is experimentally demonstrated on a SiGe-on-insulator substrate, under Si back-gate operation. Both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes. Keywords: Bilayer, n-TFET, p-TFET, SiGe, SiGe-on-insulator (SiGeOI), ZnSnO

High reactivity of H2O vapor on GaN surfaces

ABSTRACT Understanding the process of oxidation on the surface of GaN is important for improving metal-oxide-semiconductor (MOS) devices. Real-time X-ray photoelectron spectroscopy was used to observe the dynamic adsorption behavior of GaN surfaces upon irradiation of H2O, O2, N2O, and NO gases. It was found that H2O vapor has the highest reactivity on the surface despite its lower oxidation power. The adsorption behavior of H2O was explained by the density functional molecular dynamic calculation including the spin state of the surfaces. Two types of adsorbed H2O molecules were present on the (0001) (+c) surface: non-dissociatively adsorbed H2O (physisorption), and dissociatively adsorbed H2O (chemisorption) molecules that were dissociated with OH and H adsorbed on Ga atoms. H2O molecules attacked the back side of three-fold Ga atoms on the (0001̅) (−c) GaN surface, and the bond length between the Ga and N was broken. The chemisorption on the (101̅0) m-plane of GaN, which is the channel of a trench-type GaN MOS power transistor, was dominant, and a stable Ga-O bond was formed due to the elongated bond length of Ga on the surface. In the atomic layer deposition process of the Al2O3 layer using H2O vapor, the reactions caused at the interface were more remarkable for p-GaN. If unintentional oxidation can be resulted in the generation of the defects at the MOS interface, these results suggest that oxidant gases other than H2O and O2 should be used to avoid uncontrollable oxidation on GaN surfaces.

Scattering suppression at MOS interface towards high-mobility Si-based field-effect transistors

The severe scattering at metal-oxide-semiconductor (MOS) interfaces, manifesting as carrier mobility declining, is always a puzzle in the field of Si-based field-effect transistors (FETs) towards high-performance devices. In this work, an elaborate study on interfacial scattering suppression through process optimization is reported. Dry oxidation is proved to be more efficient in the construction of a damage-free oxide/semiconductor interface. Meanwhile, a thick thermal-SiO2 interlayer (i.e. a long growth time), together with a long-duration post-annealing treatment, is beneficial for interface planarization. Such an interface roughness scattering control, combined with Coulomb and defect scattering restrictions, can be realized with an optimized FET process flow. On this occasion, the as-fabricated Si MOSFETs show a higher gate-controlled drain current, and are with a peak electron mobility of ∼8372 cm2 V−1 s−1 at 1.6 K. Moreover, confined magnetotransport properties of two-dimensional electron gas are further revealed by the integer quantum Hall effects. Notably, our work presents a feasible integration flow to fabricate high-mobility Si MOS devices via scattering suppression, which may promote the evolution of Si-based MOS quantum dots for potential solid-state quantum computing.

Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.

Giant Enhancement of Radiative Recombination in Perovskite Light-Emitting Diodes with Plasmonic Core-Shell Nanoparticles.

The integration of nanoparticles (NPs) into functional materials is a powerful tool for the smart engineering of their physical properties. If properly designed and optimized, NPs possess unique optical, electrical, quantum, and other effects that will improve the efficiency of optoelectronic devices. Here, we propose a novel approach for the enhancement of perovskite light-emitting diodes (PeLEDs) based on electronic band structure deformation by core-shell NPs forming a metal-oxide-semiconductor (MOS) structure with an Au core and SiO shell located in the perovskite layer. The presence of the MOS interface enables favorable charge distribution in the active layer through the formation of hole transporting channels. For the PeLED design, we consider integration of the core-shell NPs in the realistic numerical model. Using our verified model, we show that, compared with the bare structure, the incorporation of NPs increases the radiative recombination rate of PeLED by several orders of magnitude. It is intended that this study will open new perspectives for further efficiency enhancement of perovskite-based optoelectronic devices with NPs.

Taperless Si hybrid optical phase shifter based on a metal-oxide-semiconductor capacitor using an ultrathin InP membrane.

We propose a III-V/Si hybrid metal-oxide-semiconductor (MOS) optical phase shifter using an ultrathin InP membrane, which allows us to eliminate the III-V taper required for mode conversion between Si and hybrid waveguides. We numerically revealed that thinning a III-V membrane can reduce the insertion loss of the phase shifter while maintaining high modulation efficiency because the optical phase shift is induced by carrier accumulation at the MOS interface. We experimentally demonstrated the proposed optical phase shifter with an ultrathin InP membrane and achieved the modulation efficiency of 0.54 Vcm and the insertion loss of 0.055 dB. Since the taperless structure makes the hybrid integration easier and more flexible, the hybrid MOS optical phase shifter with an ultrathin III-V membrane is promising for large-scale Si programmable photonic integrated circuits.

P-Channel TFET Operation of Bilayer Structures With Type-II Heterotunneling Junction of Oxide- and Group-IV Semiconductors

We propose a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing us to realize both n- and p-channel TFET operations under the same device structure. Here, the p-IV side in the heterostructure has a metal-oxide-semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current under the p-TFET operation. Technology computer-aided design (TCAD) simulation predicts the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. Moreover, we experimentally demonstrate the p-TFET operation of the n-ZnSnO/p-SiGe bilayer device, fabricated on a SiGe-on-insulator substrate, under Si back-gate operation. In addition, both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes.

Enhancement-Mode $\beta$ -Ga2O3 Current Aperture Vertical MOSFETs With N-Ion-Implanted Blocker

Enhancement-mode (E-mode) vertical $\beta $ -Ga2O3 metal–oxide–semiconductor (MOS) field-effect transistors featuring a current aperture were developed on a single-crystal $\beta $ -Ga2O3 (001) substrate. Nitrogen ions were implanted into a drift layer grown by halide vapor phase epitaxy to form current blocking layers (CBLs) for vertical source–drain isolation, while Si ions were implanted to form degenerately doped source contact regions and a top-gated lateral channel that was fully depleted at 0-V gate bias. The devices delivered a high output current on/off ratio of $2\times {10}^{{7}}$ despite a nonideal MOS interface that limited the maximum drain current density to <0.1 kA/cm2. Pulsed operation without current collapse under off-state voltage stress was demonstrated. Hard breakdown occurred prematurely owing to leakage through the CBLs, but is expected to improve with an optimized nitrogen implantation process. The realization of E-mode vertical Ga2O3 transistors based on a manufacturable all-ion-implanted process represents an important step toward practical applications of Ga2O3 power electronics.

Variability and Fidelity Limits of Silicon Quantum Gates Due to Random Interface Charge Traps

Silicon offers an attractive material platform for hardware realization of quantum computing. In this study, a microscopic stochastic simulation method is developed to model the effect of random interface charge traps in silicon metal-oxide-semiconductor (MOS) quantum gates. The statistical results show that by using a fast two-qubit gate in isotopically purified silicon, the two-qubit silicon-based quantum gates have the fidelity >98% with a probability of 75% for the state-of-the-art MOS interface quality. By using a composite gate pulse, the fidelity can be further improved to >99.5% with the 75% probability. The variations between the quantum gate devices, however, are largely due to the small number of traps per device. The results highlight the importance of variability consideration due to random charge traps and potential to improve fidelity in silicon-based quantum computing.

Improved characteristics of MOS interface between In0.53Ga0.47As and insulator by H2 annealing with Pt gate electrode

In this work, we fabricated n-In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) with a metal-oxide-semiconductor (MOS) interface of Y2O3/In0.53Ga0.47As. We investigated interfacial properties of the gate stack through the H2 ambient annealing process in MOSCAPs. We obtained an extremely low interface trap density of Dit = 1.8 × 1011 cm−2 eV−1. We compared the H2 annealing effect in different gate electrode materials of Ni and Pt. We determined that the Pt electrode was effective in maximizing the impact of H2 annealing. Also, we fabricated In0.53Ga0.47As-on-insulator MOS field-effect-transistors using an optimized annealing process, which showed more stable electrical characteristics than devices through the N2 ambient annealing process.

Numerical analysis of Ge/Si hybrid MOS optical modulator operating at mid-infrared wavelength

We numerically analyze an optical intensity modulator operating at a mid-infrared (MIR) wavelength based on a Ge/Si hybrid metal-oxide-semiconductor (MOS) capacitor formed by bonding a thin Ge membrane on a Si layer. Owing to the large free-carrier absorption of accumulated holes at the Ge MOS interface, the proposed optical modulator is predicted to exhibit efficient absorption modulation of >15 dB mm−1 with a 2 V amplitude of a gate voltage at a wide MIR spectrum from 2 to 7 μm. The 250 μm long device gives an optical modulation amplitude of −3 dBm, which is at least 11 dBm better than that of a Si/Si MOS Mach–Zehnder optical modulator relying on the plasma dispersion effect. The presented analysis shows the usefulness of the free-carrier absorption in Ge for an intensity optical modulator operating at a MIR wavelength.

III–V/Si Hybrid MOS Optical Phase Shifter for Si Photonic Integrated Circuits

We present a novel optical phase modulation scheme on a Si photonic platform that uses a III–V/Si hybrid metal–oxide–semiconductor (MOS) capacitor formed by bonding an n-type InGaAsP membrane on a p-type Si waveguide. We numerically revealed that the phase modulation efficiency was improved by a factor of 7–8 owing to electron accumulation at the InGaAsP MOS interface when the n-type Si layer in a Si MOS optical phase shifter was replaced by an n-type InGaAsP layer. To realize the III–V/Si hybrid MOS capacitor, we developed an Al2O3 bonding interface deposited by atomic layer deposition that enabled a low interface trap density of μ m wavelength owing to the electron-induced change in the refractive index of InGaAsP. Since no holes were induced in the III–V layer of the III–V/Si hybrid MOS capacitor, we avoided large hole-induced absorption in InGaAsP. As a result, when we had a π phase shift, we obtained optical absorption of 0.23 dB, approximately ten times smaller than that of a Si MOS optical phase shifter. We found by numerical analysis that the efficient low-loss III–V/Si hybrid MOS optical phase shifter improved markedly the optical modulation amplitude, indicating its suitability for high-speed modulation beyond 100 Gb/s. We also demonstrated a Mach–Zehnder interferometer optical switch using the proposed optical phase shifter with a switching time of less than 20 ns. We achieved an extremely low switching power of approximately 1 nW, enabling a large-scale optical switch and universal photonic integrated circuits. We also discuss the feasibility of a photonic neural network for deep learning.

High-quality SiNx/p-GaN metal-insulator-semiconductor interface with low-density trap states

We report on a high-quality p-GaN metal-insulator-semiconductor (MIS) capacitors with sharp interface morphology and the lowest interface trap density by using SiNx as the gate dielectric layer. Transmission electron microscopy and x-ray photoelectron spectroscopy (XPS) analysis revealed a high-quality interface morphology with the effective removal of carbon and oxygen impurities. Better than the interface properties of Al2O3, SiO2, and CaF2/p-GaN metal-oxide-semiconductor (MOS) or MIS capacitors, the capacitance-voltage measurements of SiNx/p-GaN showed negligible electrical hysteresis after a two-step surface pre-treatment, leading to the lowest trapped charge density of 5 × 1010 cm−2. The interface state density distribution was also reduced to be ~1–2 × 1012 cm−2 · eV−1 at Et–Ev = 0.2–0.45 eV and 3–5 × 1012 cm−2 · eV−1 near the valance-band edge after the treatments. The achievement of the high-quality MIS interface was attributed to the suppression of the Mg-Ga-O interfacial disordered layer by the effective surface treatments and oxygen-free deposition process, which was usually observed at Al2O3/p-GaN MOS interface.

Interface trap characterization of Al2O3/GaN vertical-type MOS capacitors on GaN substrate with surface treatments

We report on the interface trap properties Al2O3/GaN vertical-type metal-oxide-semiconductor (MOS) capacitors homogeneously grown on GaN substrates with different surface treatments. The electrical and microstructure characteristics are analyzed with regard to the behaviors and natures of different trap states at and close to the MOS interface. It is shown that only acid cleaning could not effectively suppress the interface traps, while a following (NH4)2S passivation drastically reduce the interface state density to the detection limit of ∼1011 cm−2eV−1. At the same time, border traps and fixed charges located close to the MOS interface are also suppressed, leading to a neglecting electrical hysteresis and frequency dispersion in the capacitance-voltage measurement.

A silicon metal-oxide-semiconductor electron spin-orbit qubit

The silicon metal-oxide-semiconductor (MOS) material system is a technologically important implementation of spin-based quantum information processing. However, the MOS interface is imperfect leading to concerns about 1/f trap noise and variability in the electron g-factor due to spin–orbit (SO) effects. Here we advantageously use interface–SO coupling for a critical control axis in a double-quantum-dot singlet–triplet qubit. The magnetic field-orientation dependence of the g-factors is consistent with Rashba and Dresselhaus interface–SO contributions. The resulting all-electrical, two-axis control is also used to probe the MOS interface noise. The measured inhomogeneous dephasing time, T_{{mathrm{2m}}}^ star, of 1.6 μs is consistent with 99.95% 28Si enrichment. Furthermore, when tuned to be sensitive to exchange fluctuations, a quasi-static charge noise detuning variance of 2 μeV is observed, competitive with low-noise reports in other semiconductor qubits. This work, therefore, demonstrates that the MOS interface inherently provides properties for two-axis qubit control, while not increasing noise relative to other material choices.

Difference of Near-Interface SiO2 Structures between O2-Oxidation and H2O-Oxidation of 4H-SiC (0001) and Its Impact on MOS Interface Characteristics

The effects of the selection of oxidant species, i.e. O2 or H2O on metal-oxide-semiconductor (MOS) interface properties on both 4H-SiC (0001) Si-face and (000-1) C-face were systematically investigated from the viewpoints of near-interface oxide microscopic structures, as well as those of electrical characteristics of MOS capacitors. As the possible origins of the significantly different MOS characteristics between dry and wet-oxidized interfaces, the differences in the strained structure of near-interface SiO2 were indicated. The important roles of both oxygen partial pressure in wet-oxidation ambient and oxidation temperature to control the MOS interface characteristics were also discussed.

Efficient low-loss InGaAsP/Si hybrid MOS optical modulator

A high-modulation-efficiency optical modulator integrated on silicon (Si) is a key enabler for low-power and high-capacity optical interconnects. However, Si-based optical modulators suffer from low phase modulation efficiency owing to the weak plasma dispersion effect in Si. Therefore, it is essential to find a novel modulation scheme that is compatible with a Si photonics platform. Here, we demonstrate an InGaAsP/Si hybrid metal-oxide-semiconductor (MOS) optical modulator with a Mach-Zehnder interferometer (MZI) formed by direct wafer bonding with an Al2O3 bonding interface. Electron accumulation at the InGaAsP MOS interface enables the extraction of the electron-induced refractive index change in InGaAsP, which is significantly greater than that in Si. The presented modulator exhibits a phase modulation efficiency of 0.047 Vcm, which is approximately 5 times higher than that of Si MOS optical modulators. This approach provides a new efficient scheme of phase modulation on a Si photonics platform for low-power, high-speed, and high-density optical links.

Investigation of origins of the critically different MOS interface characteristics between dry-oxidized and wet-oxidized silicon carbide

Design of thermal oxidation processes has a crucial role to control the metal-oxide-semiconductor (MOS) interface characteristics of 4H-SiC. The effects of the oxidant species, i.e. O2 or H2O on MOS interface properties on both 4H-SiC (0001) Si-face and (000-1) C-face were systematically investigated from the viewpoints of SiO2 growth kinetics and near-interface oxide microscopic structures, as well as those of electrical characteristics of MOS capacitors. As the possible origins of the significantly different MOS electrical properties between dry and wet-oxidized interfaces, the differences in the interface reaction mechanisms to grow SiO2 and those in the strained structure of near-interface SiO2 are indicated. The requirement for the control of O2:H2O ratio in the oxidizing ambient to optimize the MOS characteristics was also investigated.