Metal-oxide-semiconductor Interface Research Articles

Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

In contrast to high hole mobility of p-channel Ge metal–oxide–semiconductor field-effect transistors (MOSFETs), low electron mobility and poor current drive of n-channel Ge MOSFETs are one of critical issues for realizing Ge complementary metal–oxide–semiconductor (CMOS) technologies. In order to adequately understand the physical origins of the difference in the Ge MOS mobility behaviors between electrons and holes, an appropriate mobility analysis is strongly needed. In this paper, we propose a novel method to extract both electron and hole mobility in an identical device by using metal source/drain (S/D) Ge-on-insulator (GOI) MOSFETs. The influence of the parasitic resistance associated with metal S/D junctions is eliminated by using MOSFETs with four-terminal Kelvin patterns. It is demonstrated that the electron and hole mobility at the same Ge MOS interfaces are accurately determined. It is found, as a result, that the present Ge n-channel MOSFET has the electron mobility close to the Si universal electron mobility. On the other hand, the hole mobility at the same MOS interface is lower than the Si universal hole mobility, which is attributable to low crystal quality of the channel and/or the poor MOS interface properties. These facts strongly suggest the low electron mobility in Ge MOSFETs, reported so far, is not necessarily limited by any essential problems, but much higher electron mobility is expected by further improvement of the material and interface qualities.

Investigation of InAlAs Oxide/InP Metal–Oxide–Semiconductor Structures Formed by Wet Thermal Oxidation

This study presents III–V metal–oxide–semiconductor (MOS) structures formed by the wet thermal oxidation of an epitaxial InAlAs layer grown on an InP substrate. Since the III–V compounds require a lower process temperature than that of the standard Si complementary MOS process, the InAlAs oxide layer was formed by wet thermal oxidation at 525 °C. The composition of the oxide layer evaluated by X-ray photoelectron spectroscopy (XPS) revealed that the oxide layer was composed of In, Al, and P oxides without any As oxide. The InAlAs oxide/InP MOS capacitors showed well-behaved capacitance–voltage (C–V) curves with a small frequency dispersion. The MOS interface properties were evaluated by the conductance method, and the minimum interface trap density of around 1012 cm-2 eV-1 was obtained.

InAs nanowire metal-oxide-semiconductor capacitors

We present a capacitance-voltage study for arrays of vertical InAs nanowires. Metal-oxide-semiconductor (MOS) capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr∕Au metallization as one of the capacitor’s electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.

Field-effect mobility temperature modeling of 4H-SiC metal-oxide-semiconductor transistors

Here a physically based channel mobility model has been developed to investigate the temperature dependence of the field-effect mobility of 4H-SiC metal-oxide-semiconductor (MOS) transistors with thermally oxidized gate insulators. This model has been designed so that it accounts for the high density of traps at the MOS interface. This temperature dependence is a key issue for silicon carbide electronics, as its basic material properties make it the foremost semiconductor for high power/high temperature electronic devices in applications such as spacecraft, aircraft, automobile, and energy distribution. Our modeling suggests that the high density of charged acceptor interface traps, encountered in thermally grown gate oxides, modulates the channel mobility due to the Coulomb scattering of free carriers in the inversion layer. When the temperature increases, the field-effect mobility of these devices also increases, due to an increase in inversion charge and a reduction of the trapped charge. Experimental data of the field-effect mobility temperature dependence are in good agreement with this model.

Interface Properties of Metal–Oxide–Semiconductor Structures on 4H-SiC{0001} and (1120) Formed by N2O Oxidation

4H-SiC(0001), (0001), and (1120) have been directly oxidized by N2O at 1300°C, and metal–oxide–semiconductor (MOS) interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC(0001), (0001) and (1120) faces have shown effective channel mobilities of 26, 43, and 78 cm2/Vs, respectively. Secondary ion mass spectrometry analyses have revealed a clear pileup of nitrogen atoms near the MOS interface. The thickness of the interfacial transition layer can be decreased by N2O oxidation. The crystal face dependence of the interface structure is discussed. A simple consideration of chemistry indicates that NO, generated from the decomposition of N2O, may be a more efficient oxidant of carbon than O2.

Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy

The degradation phenomena in polycrystalline-silicon thin film transistors fabricated by a low-temperature process below 425°C (low-temperature-processed poly-Si TFTs) have been investigated. The types of degradation caused by self-heating and hot carriers have been classified, and these degradation phenomena have been investigated using emission light microscopy. Self-heating degradation is thought to originate in the breaking of Si–H bonds and regeneration of dangling bonds in the metal–oxide–semiconductor (MOS) interface and channel poly-Si layers. On the other hand, hot carrier degradation is considered to originate from the damage of the MOS interface and of the channel poly-Si layer near the drain of TFTs. When the gate stress voltage is equal to the threshold voltage, maximum degradation is induced because both the electric field near the drain in the channel and the electron density increase. Results of emission light spectra measurements confirmed the generation of high-energy carriers under this stress.

Advances in SiC power MOSFET technology

In recent years, SiC has received increased attention because of its potential for a wide variety of high temperature, high power, high frequency, and/or radiation hardened applications under which conventional semiconductors cannot adequately perform. For semiconductor devices designed to operate in these harsh conditions, SiC offers an unmatched combination of electronic and physical properties. The availability of SiC wafers on a commercial basis has led to the demonstration of many types of metal-oxide semiconductor (MOS)-gated devices that exploit its unique properties. To which extent the potential of SiC power MOSFET can be utilized is a question of appropriate SiC polytype, device structure, MOS interface quality and maturity of the technology. This paper reviews the present status of the SiC power MOSFETs technology that is approaching commercialization. Emphasis is placed upon the impact of SiO 2–SiC interface quality on the performance of SiC MOSFETs.

Analysis of interface roughness’s effect on metal–oxide–semiconductor Fowler-Nordheim tunneling behavior using atomic force microscope images

For the first time, metal–oxide–semiconductor interface atomic force microscope images were used to directly calculate the Fowler-Nordheim tunneling behavior for thin gate oxides with different interface roughness. Assuming that the roughness is conformal on both interfaces, surface curvature and electric field distribution were used to calculate the tunneling current density caused by low spatial frequency roughness. On the other hand, a three-dimensional Laplace solver and a quasi-one-dimensional Fowler-Nordheim equation were used to calculate the tunneling current contributed by high spatial frequency roughness. Considering contributions due to both high and low spatial frequency roughnesses, we found good agreement between the theoretical calculation and experimentally measured tunneling current–voltage curves. This simulation indicates that oxide thinning is probably not the main reason for the increase of tunneling current in the thin oxide (∼6 nm) range. The higher surface electric field due to roughness curvature itself is most likely responsible for this increase.

MOS interface characterization by cross-sectional STM

The application of the cross-sectional scanning tunneling microscope (XSTM) to the interface observation of metal-oxide—semiconductor (MOS) structure formed on Si(111) was described. The STM images revealed the morphology of the MOS interface region where the cleaved Si part showed a novel reconstructed structure of Si(111)-8 × 1 and the metal (Au) layer of ∼ 10 nm higher from the Si portion was fractured during the cleaving process. Scanning tunneling spectroscopy (STS) measurement on the Si part showed systematic shifts of the spectra with the application of the bias voltages between the metal and the Si, which agreed well with the expected band bending in the Si qualitatively.

Cross-Sectional Scanning Tunneling Microscopy on Cleaved Si(111): Observation of Novel Reconstruction and Structural and Electrical Properties of MOS Interface

Cross-sectional scanning tunneling microscopy (XSTM) measurements revealed two types of reconstructions on Si(111) surfaces depending on the cleaving conditions. The first one is a 2×1 structure consistent with previous reports. The second one is a novel 8×1 structure, which shows a missing-row structure where one row is missing in every four rows in the 2×1 structure. We propose a model for the missing-row reconstruction seen on the Si(110) surface. XSTM observation of the metal-oxide-semiconductor (MOS) interface structure clearly showed a fractured metal layer and cleaved Si areas which demonstrated the possibility of observing the interface with atomic resolution. Scanning tunneling spectroscopy (STS) measurement of the Si part showed systematic shifts of the spectra with the application of bias voltage between the metal and the Si, which agreed well with the expected band bending in the Si.

Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface

The response time of deep-lying interface states in silicon carbide metal-oxide semiconductor (MOS) capacitors may be thousands of years at room temperature. To accurately measure interface state density beyond about 0.6 eV from the band edge, it is necessary either to raise the temperature well above 300K so that all states can follow changes in DC bias, or to utilize photoexcitation to modulate the interface state population at room temperature. In this paper, we use the hilo capacitance-voltage technique and the ac conductance technique at elevated temperatures to characterize the MOS interface of p-type 6H-SiC. We report on the effect of surface cleaning and push/pull rates, and give the first detailed comparison of the effect of aluminum vs boron as the p-type dopant on the MOS interface. Oxides grown on 6H-SiC at 1150°C in wet O2 followed by a 30 min insitu argon anneal have fixed charge densities as low as 9 x 1011 cm-2 and interface state densities as low as 1.5 x 1011 cm-2 eV-1.

Characterization of the effects of different capping layer structures on the laser recrystallization of silicon by using electrical test structures and Raman spectroscopy

Polycrystalline silicon on insulator is laser-recrystallized using three different capping layer structures on separate wafers. The capping layer structures used include a 6-nm nitride layer, a combination of 64-nm nitride and 20-nm oxide layers, and 50-nm nitride antireflection periodic stripes oriented parallel to the direction of laser scanning. Electrical characteristics are measured by metal-oxide-semiconductor (MOS) silicon-on-insulator (SOI) test structures fabricated in the laser-recrystallized silicon films. Measurement of carrier mobilities, MOS interface properties, leakage currents, and ring oscillator delay times are compared for wafers having different capping layer structures. Stress in each case is characterized using a Raman spectrometer with microprobe.

Au and Al interface reactions with SiO2

The chemical bonding, extent, and evolution of metal-oxide semiconductor interface regions have been probed with soft-x-ray photoemission spectroscopy following room-temperature, in situ metallization. We identify strong atomic rearrangement and charge transfer at metal-SiO2 interfaces. The quantitatively different processes found for Au and Al suggest new structural models. For Al-SiO2, Al first clusters about each surface O and then grows Al2O3 by reducing SiOx (X < 2) and leaving excess Si at the interface. In contrast, Au forms islands on SiO2 with evidence of Au–Si bonding, causing an SiOx layer beneath the contact.