Abstract
The paper proposes a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing for both n- and p-channel TFET operations under the same device structure. The p-IV side in the heterostructure has a metal-oxide-semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current during p-TFET operation. Technology computer-aided design (TCAD) simulation is used to predict the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. The p-TFET operation of the n-ZnSnO/p-SiGe bilayer device is experimentally demonstrated on a SiGe-on-insulator substrate, under Si back-gate operation. Both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes. Keywords: Bilayer, n-TFET, p-TFET, SiGe, SiGe-on-insulator (SiGeOI), ZnSnO
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