Metal Oxide Semiconductor Devices Research Articles

High-performance Te-doped p-type MoS2 transistor with high-K insulators

Molybdenum disulfide (MoS2) films possess intrinsic n-type conductivity, and thus development of p-type MoS2 films for realizing practical next-generation complementary metal oxide semiconductor devices is extremely challenging. The use of dopants is a well-known conventional approach for engineering intrinsic conductivity with improved device performance. Herein, we demonstrate the n-type conductivity suppressing property of the tellurium (Te)-doped multilayer MoS2, grown by metal-organic chemical vapor deposition. The back-gated as-grown Te-doped multilayer MoS2 field-effect transistor (FET) is observed to exhibit p-type behavior with a maximum mobility of 0.036 cm2/V·s, ON/OFF current ratio of 7.8×103, and a Schottky barrier height of 32 meV. A quantitative Schottky barrier height of a p-type multilayer MoS2-based FET with Au electrode has been obtained by analyzing its low-temperature transport characteristics. Enhanced device performance has been achieved by doping the p-type MoS2 transistors in a back-gate structure and high-K dielectric gate insulators with Te. pFET devices containing Al2O3 dielectric insulators exhibit extremely high performance, including a maximum mobility of ∼182 cm2/V·s, maximum ON/OFF current ratio of ∼105, and a low subthreshold swing of ∼215 mV/dec. These improvements have been attributed to the charge screening effect associated with the high-K dielectrics and a low Schottky barrier height.

In situ thermal runaway of Si-based press-fit diodes monitored by infrared thermography

Overvoltage is one of the main causes that lead to the failure of electronic devices. This makes fundamental to understand the electrical and thermal mechanisms engaged in the process. In this work, the influence of the semiconductor technology on the thermal runaway involved in the dielectric breakdown of commercial press-fit diodes, operating in reverse conditions, has been studied. Infrared thermography has been used to monitor the temperature evolution before, during and after the failure. Schottky and Metal oxide semiconductor devices, based on Si, have been evaluated following this methodology. The current flowing through the diode causes its temperature to rise, which increases the current with a further increase in temperature that triggers the avalanche process. The diode configuration conditions the heating associated with the spark appearing during the breakdown. This process is faster for Schottky diodes than for Metal oxide semiconductors, leading to higher temperatures. Besides, mechanical breaking is observed in the semiconductor due to the stresses generated during the fast heating-cooling processes after the different breakdowns events. The reached temperatures are enough to melt the solder that creates an electrical path, which short-circuits the diodes and leads to their final failure. These differences in the failure behavior must be taken into account to choose the adequate technology in practical applications.

A Review on the Recent Advancements in Tin Oxide-Based Thin-Film Transistors for Large-Area Electronics

Amorphous oxide semiconductors have gained significant attention in the past few decades and have emerged as a promising material for thin-film transistors (TFTs) because they offer high carrier mobility (> 10–50 cm2/V s) and uniformity. In particular, amorphous indium-gallium-zinc-oxide (a-IGZO) has been widely employed as an active channel material in TFTs owing to its high mobility. However, indium-based TFTs suffer from stability problems under positive, negative, and illumination bias stress conditions, which limits their applications in flat-panel displays. Moreover, the limited supply of indium and growing demand for high-stability TFTs with better electrical performance has led to the introduction of tin oxide as a promising solution to replace indium in TFTs. This review provides an overview on the progress and recent developments in indium-free tin oxide-based TFTs for large-area electronics, with special emphasis on the sputtering technique. In addition, the source of the dual conductivity of tin oxide is addressed, which will be helpful in designing complementary metal oxide semiconductor devices. The instability problems and approaches to improve the electrical performance of tin oxide TFTs are also discussed.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) devices are expected to face new challenges such as exponential current leakage, DIBL, hot carrier effects, and etc. at nano scale. Hence the CMOS technology is being supplanted by the nanotechnologies. Quantum-dot Cellular Automata (QCA) is key technology at nano scale which operates at tera hertz of speed. Comparing with the traditional CMOS technology, the QCA technology has low power consumption and high density. This technology also has a unique methodology such as “processing in wire” and “memory-in-motion”. This work confers an area proficient, high speed full adder (FA) design with efficient clocking. The proposed full adder design comprises of 26 Quantum cells with delay of two clock phases, area occupancy of 0.03 µm 2 . This paper utilizes the unique characteristics of QCA and the proposed Wallace tree multiplier is implemented with the mentioned FA and is designed by using QCA Designer 2.0.3 tool.

Experimental and theoretical study of capacitive memory of metal-oxide-semiconductor devices based on Er-doped In2O3 nano-column arrays

The enhanced electronic memory performance of glancing angle deposited erbium-doped indium oxide (In2O3:Er) transparent nano-column (NCol) based metal-oxide-semiconductor (MOS) structured memory devices is reported. The fabricated MOS devices are Au/In2O3/p-Si, Au/0.26 at. % In2O3:Er/p-Si, and Au/0.48 at. % In2O3:Er/p-Si. The capacitance–voltage (C–V), conductance–voltage (G–V), C–V hysteresis, endurance, and retention properties from the cyclic current–voltage (I–V) curve of the fabricated devices were investigated in detail. The overall interface state density (Dit) for the devices at the different applied frequency (f) decreases with the increase in Er doping. The observations obtained from C–V, G–V, and Dit–f curves were theoretically explained considering a modified delta depletion model. It was found that Au/0.48 at. % In2O3:Er/p-Si does not go to inversion even at a high applied voltage. The constant capacitive memory window (MW) for Au/In2O3/p-Si is ∼1 V at the depletion region. MW increases from ∼0.6 V (sweep voltage ±6 V) to ∼2.5 V (sweep voltage ±16 V) and ∼1.4 V (sweep voltage ±6 V) to ∼6.8 V (sweep voltage ±16 V), respectively, for Au/0.26 at. % In2O3:Er/p-Si and Au/0.48 at. % In2O3:Er/p-Si. The increased MWs despite reduced Dit is explained in detail by primarily considering increased polarization switching of the In-O-Er material, asymmetric charge injection from the top electrode, and the presence of the oxygen-rich environment. The I–V hysteresis performance of the devices under a reverse bias was also improved with Er doping due to the migration of O2− inside the oxide layer. The whole analysis indicates that the gate-controlled Au/0.48 at. % In2O3:Er/p-Si MOS device is appropriate for capacitive memory applications.

Fast Characterization of Input-Output Behavior of Non-Charge-Based Logic Devices by Machine Learning

Non-charge-based logic devices are promising candidates for the replacement of conventional complementary metal-oxide semiconductors (CMOS) devices. These devices utilize magnetic properties to store or process information making them power efficient. Traditionally, to fully characterize the input-output behavior of these devices a large number of micromagnetic simulations are required, which makes the process computationally expensive. Machine learning techniques have been shown to dramatically decrease the computational requirements of many complex problems. We use state-of-the-art data-efficient machine learning techniques to expedite the characterization of their behavior. Several intelligent sampling strategies are combined with machine learning (binary and multi-class) classification models. These techniques are applied to a magnetic logic device that utilizes direct exchange interaction between two distinct regions containing a bistable canted magnetization configuration. Three classifiers were developed with various adaptive sampling techniques in order to capture the input-output behavior of this device. By adopting an adaptive sampling strategy, it is shown that prediction accuracy can approach that of full grid sampling while using only a small training set of micromagnetic simulations. Comparing model predictions to a grid-based approach on two separate cases, the best performing machine learning model accurately predicts 99.92% of the dense test grid while utilizing only 2.36% of the training data respectively.

Electrical characterization of near-interface traps in thermally oxidized and NO-annealed SiO2/4H-SiC metal-oxide-semiconductor capacitors

Conductance method and capacitance-voltage (C-V) measurements are used to detect and analyze the characteristics of traps in thermally oxidized and NO-annealed SiO2/4 H-SiC-based metal-oxide-semiconductor (MOS) structures, which have energy levels near the conduction band edge (EC) of 4 H-SiC. The near-interface traps (NITs) located within SiO2 near the SiO2/4 H-SiC interface, which have a strong effect on the mobility and reliability of the MOS devices, are separated from the interface traps. According to the bias state of the MOS capacitors, two types of electron exchange mechanisms between the energy level of NITs and EC of 4 H-SiC are proposed. The influence of NITs on the (C-V) and conductance characteristics of the MOS capacitors is studied. The possible effect of NITs on the performance of electronic devices containing a MOS capacitor is predicted.

Negative resistance, capacitance in Mn/SiO2/p-Si MOS structure

In this work is that we have manufactured a new structure that had not been studied by researchers before. This structure is Mn/SiO2/Si was synthesised by liquid phase epitaxy (LPE) as a metal-oxide- semiconductor (MOS) and can be used as a tunneling diode; demonstrated from I–V measurement and negative resistance. The structure and its characterization were examined by scanning electron microscope, XRD diffraction, C-V and I–V measurements. We studied the temperature, voltage dependence of dielectric and electrical parameters of the fabricated Mn/SiO2/P-Si MOS device. I–V measurements for this structure display diode tunnel behavior with negative resistance. Parameters such as series resistance (Rs), permittivity (ε′), dielectric loss (ε″), a tangent of the dielectric loss factor (tan δ), real and imaginary parts of electrical modulus (M′ and M″) and ac conductivity were examined in a temperature range of 303–393 K and frequency range (10 Hz–20 MHz) under 1 Vrms applied voltage along with dc bias range of (−2.0–2.0 V). We found that thermal reordering of the interface is a reason for a continuous density distribution of interface states with homogenous relaxation time, which in turn induced a higher sensitivity to both C and G/w response with electric field frequency. The device showed negative values for capacitance (C), dielectric loss (ε″), and dielectric loss tangent (tan δ) at all temperatures.

Effects of series resistance and interface state on electrical properties of Al/Er2O3/Eu2O3/SiO2/n-Si/Al MOS capacitors

Advances in Metal-Oxide-Semiconductor (MOS) capacitors fabrication and processing techniques have significantly reduced the adverse effects of processing on the disruption of the ideal MOS devices. However, changes in interface state density and series resistance have remained significant issues for the performance of MOS devices. In this paper, the impacts of multi-layers on the electrical interface states and series resistance characteristics of Al/Er2O3/Eu2O3/SiO2/n-Si/Al MOS capacitors is reported, by analyzing Capacitance – Voltage (C – V), conductance (G/ω – V), series resistance, and interface states density. Ideal characteristics have been observed for obtained series resistance (Rs) and interface state density (Dit), and the calculated values of Dit are in order of (1010 eV2Cm−2). The outcomes have demonstrated that the Rs and the Dit are essential factors that influence the electrical characteristics of the MOS capacitors. Furthermore, interfacial layers are the cause of variations in the Rs and Dit.

Plasma-enhanced atomic layer-deposited La2O3 ultra-thin films on Si and 6H–SiC: a comparative study

The rare earth La2O3 is always a material of interest and has a potential to replace SiO2 in metal oxide semiconductor devices. In this context, we investigated the structural and electrical properties of La2O3 ultra-thin films grown by indigenously developed plasma-enhanced atomic layer deposition on Si and 6H–SiC substrates. The tris(cyclopentadienyl)lanthanum III precursor and O2 plasma as an oxidant were used as starting materials. The deposited La2O3 ultra-thin films were characterized by means of X-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, atomic force microscopy and X-ray diffraction. The growth rate of 0.5 ± 0.05 Ǻ per cycle was determined from optimized process parameters. The XPS and XRD results show the formation of lanthanum silicate on Si, while no formation of silicate was found on SiC. Leakage current densities of 9.58 × 10–3 A/cm2 and 2.07 A/cm2 at a bias voltage of 1 V have been determined for the Au/Cr/La2O3/Si and Au/Cr/La2O3/SiC capacitors, respectively.

Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions

Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.

Surface passivation via two-step grown nitrogen infused oxidation derived quaternary AlxZr1−xOyNz

High dielectric constant (k) quaternary AlxZr1-xOyNz was fabricated for silicon (Si)-based metal–oxidesemiconductor (MOS) devices via nitrogen infused oxidation at 600 °C. A higher k value (30.2) was attained due to accumulation of nitrogen at the oxide-Si interface to impede interfacial layer formation, yielding a reduced average oxide thickness. The presence of nitrogen was verified via detection of absorption spectra for Si-N and Si-N-Si. Interface quality of AlxZr1−xOyNz was investigated using Terman’s, high-low frequency, and conductance methods. The acquisition of low effective oxide charge and slow trap density further supported that AlxZr1−xOyNz possessed good passivation property for potential use in MOS devices.

An innovative TCAD simulated UHV-PLDMOS device with improved HTRB performance

This study proposed an innovative TCAD simulated ultra-high voltage p-type laterally diffused metal oxide semiconductor device structure with metal II field plate optimization (metal II is the second metal used on top of metal I with 10 000 Å Oxide dielectric in between as shown in figure ), which could improve high-temperature reverse-bias (HTRB) performance. By optimizing the metal II field plate position, the exposed area could be minimized, and furthermore, after using the passivation layer of oxide-(a-Si: H)-oxide-(a-Si: H)-nitride after stress, the hole trap concentration was much lower than that in the silicon nitride and silicon dioxide passivation region because of the low mobility of (a-Si: H), which was 1 cm2 v−1 s−1. The new passivation layer maintained the original p-drift reduced surface field (RESURF) doping profile and exhibited less degradation in terms of losing positive ions from the p RESURF channel crossing oxide and entering the traps. The five layers exhibited fewer traps; therefore, the degradation was improved. The reliability of the device could be increased by changing the doping concentration of the drift region according to the RESURF principle. In addition, this study compared two passivation layers of (oxide–silicon nitride) and five passivation layers of oxide- (a-Si: H)-oxide- (a-Si: H)-nitride.

Thin film deposition research and its impact on microelectronics scaling

Throughout his career, Dr. Stephen Rossnagel and his co-workers have had a profound influence on thin film deposition. His seminal work includes the development of reactive, collimated, and ionized methods of DC and RF magnetron sputtering, as well as plasma-enhanced atomic layer deposition. Most importantly, his contributions have been widely adopted within the microelectronics community in its efforts to produce finer layers with increased uniformity and functionality. While applications span a very broad range, from complementary metal oxide semiconductor device metallization to DNA sensing, Dr. Rossnagel has also conducted fundamental investigations into microstructural effects on electronic scattering. In this manuscript, the authors will highlight some of Steve’s contributions to these areas and their continued relevance to current and future microelectronic device scaling.

Size-tunable electroluminescence characteristics of quantum confined Si nanocrystals embedded in Si-rich oxide matrix

Tunable electroluminescence properties of size-controlled Si nanocrystals embedded in silicon rich oxide films are demonstrated at room temperature, using an active light emitting layer in the metal oxide semiconductor device structure. Plasma enhanced chemical vapor deposited Si-rich oxide films were annealed at elevated temperatures to form Si nanocrystals of varying diameters. A typical redshift in the photoluminescence peak is observed with increasing annealing temperature, confirming the formation of quantum confined Si nanocrystals. The carrier transport and light emission mechanism have been studied in detail through current–voltage characteristics and ultrafast transient spectroscopy, respectively. The origin of electroluminescence and the size-tunable emission peak have been analyzed and attributed to the radiative recombination of carriers within Si nanocrystal quantum wells. The fabricated Si nanocrystal-based metal oxide semiconductor light emitting diode and the resultant size-dependent tunable electroluminescence are very attractive as a potential CMOS compatible optical source for future photonic integrated chips.

Flexible Metal Oxide Semiconductor Devices Made by Solution Methods.

For the fabrication of next-generation flexible metal oxide devices, solution-based methods are considered as a promising approach because of their potential advantages, such as high-throughput, large-area scalability, low-cost processing, and easy control over the chemical composition. However, to obtain certain levels of electrical performance, a high process temperature is essential, which can significantly limit its application in flexible electronics. Therefore, this article discusses recent research conducted on developing low-temperature, solution-processed, flexible, metal oxide semiconductor devices, from a single thin-film transistor device to fully integrated circuits and systems. The main challenges of solution-processed metal oxide semiconductors are introduced. Recent advances in materials, processes, and semiconductor structures are then presented, followed by recent advances in electronic circuits and systems based on these semiconductors, including emerging flexible energy-harvesting devices for self-powered systems that integrate displays, sensors, data-storage units, and information processing functions.

Memristor based Non Volatile Random Access Memory Cell by 45nm CMOS Techology

Rapid memories receives time to live attentive of substantial concluding mission available overstretched. Objectives of principle memory innovation is to create a excessive piece thickness part. Presents new problems in extremely large scale integrated (VLSI) circuit plan. Worldwide inconstancy to accomplish excessive return SRAM objects. Semiconductor reminiscence gadgets are commonly classified as risky or non-unpredictable arbitrary get right of entry to reminiscences. SRAM is delegated an unpredictable reminiscence because it is predicated on the usage of steady capability to hold up the placed away information. In the event that the pressure is interfered with, the reminiscence substance are decimated besides if a again-up battery stockpiling framework is saved up. In this mission a non-unpredictable SRAM cellular is planned utilising a blend of memristor and metal-oxide semiconductor devices. The records is placed away inside the reminiscence in any occasion, while the pressure is killed for an inconclusive time. The precept highlight of the proposed circuit element is its non-instability.

Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer

Effects of interfacial layer on p-substrate germanium (pGe) metal oxide semiconductor (MOS) device were studied in this work. Although excellent characteristics in n-substrate Ge MOS device were reported, pGe MOS device often suffers a poor interface quality and large gate leakage current, while the equivalent oxide thickness (EOT) is scaled down below 1 nm. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed to replace the traditional germanium dioxide thanks to its good thermal stability. As a result, the pGe MOS device with HfN IL exhibits a low EOT of 0.58 nm, a low leakage current density of 2.4 × 10−4 A/cm2, a lower hysteresis value of 150 mV, a better frequency dispersion, and lower oxide/border traps. Therefore, HfN is a promising IL to achieve high performance pGe MOS device.

Utilization of nanoporous biosilica of diatoms as a potential source material for fabrication of nanoelectronic device and their characterization

Biosilica obtained from frustules of diatoms have very delicate nanostructures similar to many micro- and nanofluidic devices. In the present investigation, a cheaper and ecofriendly metal-oxide-semiconductor (MOS) tool has been fabricated exploiting frustules of the diatom Halamphora subturgida. The structural, optical, and chemical characterizations of the cleaned frustules of cultured diatom were investigated through various techniques. Electron microscopic images revealed intricate morphology of the nanostructured silica with very minute pores making the frustules very hard but light material. UV-Vis spectroscopy showed maximum absorbance at 223 nm. The absorption maximum for photoluminescence was centered at 462 nm and that of cathodoluminescence was at 439.9 nm and 466.6 nm. Bulk of extracted silicon dioxide (SiO2) nano-powder from diatom frustules was used as a source material for preparing a high-quality crystalline film on P-type silicon (p-Si) by vapor-liquid-solid (VLS) method. The crystalline quality of the film was tested by X-ray diffraction (XRD) and the crystalline size obtained was 62 ± 2.4 nm. From scanning electron microscopic (SEM) investigation, the growth of a continuous film from diatom biosilica on p-Si substrate was revealed. The thickness of the as-grown SiO2 film was 22.2 ± 1.6 nm, obtained from spectroscopic ellipsometry (SE) study. The performances of fabricated Al/SiO2/Si metal-oxide-semiconductor capacitor were tested by measuring leakage current (~ 43 ± 8 × 10−11 A μm−2 at +2 V), capacitance-voltage, constant current (0.1 μA), and voltage stress (at − 2 V) for reliable gate dielectrics applications in MOS devices. Overall, the process was cost-effective and provides an alternative technique to design high-quality diatom-derived “Bio-SiO2 films” on p-Si substrate.

Towards Ultra-Low Specific Contact Resistance on P-Type and N-Type Narrow Bandgap GeSn Semiconductors

GeSn alloys are group IV semiconductors that have attracted remarkable interest owing to their ability of strain and bandgap engineering by controlling the Sn content, their compatibility with the Si CMOS platform and their tunable and direct band gap. These material properties make GeSn a promising candidate for many electronic and optoelectronic applications including among others tunnel field effect transistors, infrared (IR) photodectors, and IR emitters. However, in order to produce high quality GeSn devices to enable these applications, it is of paramount importance to develop ohmic metal contacts with very low specific contact resistivity on both n-type and p-type doped GeSn layers used in these devices. This could be achieved by realizing high doping levels and attaining low intrinsic barrier heights between the metal and the contacted GeSn layer.The growth of metastable GeSn semiconductors is typically performed at temperatures well below 400 ºC to avoid Sn segregation and phase separation, which would compromise the opto-electronic properties of the material. [1] Therefore, major care is required when developing post-growth processes that are commonly required for device fabrication. For instance, ohmic contact formation using the conventional process of rapid thermal annealing of nickel contacts cannot be made and the GeSn cannot be cured after dopant implantation because of the very limited thermal budget. We investigated both the epitaxial growth of highly doped layers, as well as the passivation of undoped GeSn samples in order to circumvent these limitations and achieve the desired barrier heights for both p-type and n-type GeSn while varying the Sn content.First, epitaxially grown GeSn layers with p- and n-type doping are demonstrated. For GeSn doping, the CVD growth of in-situ doped GeSn layers is done using B2H6 for p-type, and AsH3 for n-type. We show high active doping levels in the orders of 1019 and 1020 cm-3 for both p-GeSn and n-GeSn, respectively. These results were obtained from the capacitance voltage measurements (CV) using metal oxide semiconductor (MOS) back-to-back devices. In addition, secondary ion mass spectroscopy (SIMS) and atom probe tomography (APT) data support the high and uniform doping levels.Secondly, since the strong Fermi level pinning (FLP) of Ge is a major problem in the development of n-type contacts due to the loss of metal work function modulation of the barrier height [2], it is expected that the GeSn materials system with low Sn levels exhibits the same behavior, thereby degrading the properties of direct metal/n-GeSn contacts. Therefore, we develop processes aiming to release the Fermi level pinning at metal/GeSn interface, thus restoring the metal work function control of the barrier height. Samples used in this study are CVD grown intrinsic GeSn relaxed samples with increasing Sn concentrations up to 11 at. %. These samples are unintentionally p-type with defect doping levels in the order of 1017 cm-3 as obtained by CV measurements on MOS devices. Our process starts by chemical passivation of these samples, then the deposition and patterning of four metals with different work functions close to the band gap is realized to obtain transfer length method (TLM) structures used for current-voltage (IV) measurements. We then extract the contact properties of these devices and estimate the change of the barrier height induced by the chemical passivation due to the depinning of the FL. This demonstrates the potential use of our process in the fabrication of future metal/n-GeSn contacts. Acknowledgements O.M. acknowledges support from NSERC Canada (Discovery, SPG, and CRD Grants), Canada Research Chairs, Canada Foundation for Innovation, Mitacs, PRIMA Québec, and Defence Canada (Innovation for Defence Excellence and Security, IDEaS).