Metal Nanocrystal Memory Research Articles

Forming Fe nanocrystals by reduction of ferritin nanocores for metal nanocrystal memory

To fabricate metal nanocrystal (NC) memories based on iron ferritin proteins, we propose a method for embedding ferritin cores in SiO2 and performing a reduction process by rapid thermal annealing (RTA) in a hydrogen atmosphere. An iron oxide core biochemically synthesized by ferritin was used to fabricate a high-density memory node array of 7.7 × 1011 dots/cm2. Reduction intermediates and metallic iron NCs were obtained in a short time by using a hydrogen atmosphere RTA with the iron oxide core embedded in SiO2. Metal-oxide-semiconductor memory structures were fabricated, capacitance–voltage (C–V) measurements were performed, and hysteresis (memory window) suggesting charging and discharging of NCs was observed. Furthermore, the memory window and the charge injection threshold tended to vary depending on the reduction temperature. Since these values are proportional to the magnitude of the dot work function (or electron affinity), it is assumed that the formation of reduced intermediates NCs with varying work functions depending on the treatment temperature affects the electrical properties. The results suggest that the work function of the charge retention node can be controlled by reducing the metal oxide, enabling a new approach to memory design that actively employs the reduction process.

Study of Memory Performance and Electrical Characteristics for Metal Nanocrystal Memories

Using a transient electrical model, in which the impacts of Si surface potential and thermal excitation were taken into account, the charging and discharging processes in a metal nanocrystal (NC) memory were simulated. For an NC memory with 2.25 nm tunnel oxide layer, the retention time is more than ten years, and the program and erase time can reach 45 and 60 μs at ±10 V applied voltage, respectively. Moreover, the carrier storage effect caused by NCs has great influence on capacitance-voltage (C-V) characteristics. The flat-band voltage shift ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> and the charge density Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nc</sub> are greatly dependent on the start sweep gate voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and the sweep rate dV/dt. The large memory window reveals the high carrier injection efficiency for both electrons and holes, and it increases steadily from 0.86 to 8.30 V with the increase of the start applied gate voltage from ±2 to ± 6 V. When the sweep rate is slow enough, the flat-band voltage shift and the stored charges will reach a saturation state. Hence, the simulation C-V characteristics of metal NC memory may guide the devices design or to predict their performances.

Metal nanocrystal memory with sol–gel derived HfO2 high-κ tunnel oxide

An all-solution processed metal–oxide–semiconductor (MOS) capacitor structure containing gold (Au) nanoparticles (NPs) within HfO2 high-κ oxide was fabricated. The ultra-thin (~10nm) HfO2 high-κ tunnel oxide layer was prepared by sol–gel process and showed good electrical properties, which were critical to superior memory property of the MOS structure. Au NPs with particle size of about 3.3nm were synthesized by chemical reduction method and then self-assembled onto HfO2 tunnel oxide. Finally, a Si/HfO2/Au NPs/HfO2 memory structure was constructed after the substrate had been covered with a sol–gel-derived HfO2 control oxide layer (~13nm). By utilizing high-quality HfO2 as tunnel oxide, the MOS structure containing Au NPs showed memory effect even at a low voltage of ±3V. Although its memory window was only 0.8V by a swapping voltage between ±5V, the MOS showed desirable retention characteristics. Therefore, we have fabricated nanocrystal memory device with sol–gel derived HfO2 high-k tunnel oxide which are attractive for low operation voltage non-volatile memory applications.

Metal Nanodot Memory by Self-Assembled Block Copolymer Lift-Off

As information technology demands for larger capability in data storage continue, ultrahigh bit density memory devices have been extensively investigated. To produce an ultrahigh bit density memory device, multilevel cell operations that require several states in one cell have been proposed as one solution, which can also alleviate the scaling issues in the current state-of-the-art complementary metal oxide semiconductor technology. Here, we report the first demonstration of metal nanodot memory using a self-assembled block copolymer lift-off. This metal nanodot memory with simple low temperature processes produced an ultrawide memory window of 15 V at the +/-18 V voltage sweep. Such a large window can be adopted for multilevel cell operations. Scanning electron microscopy and transmission electron microscopy studies showed a periodic metal nanodot array with uniform distribution defined by the block copolymer pattern. Consequently, this metal nanodot memory has high potential to reduce the variability issues that metal nanocrystal memories previously had and multilevel cells with ultrawide memory windows can be fabricated with high reliability and manufacturability.

Design of gate stacks for improved program/erase speed, retention and process margin aiming next generation metal nanocrystal memories

In this work, gate stacks in metal nanocrystal (NC) memories, as promising next generation storage devices and their systems, are extensively investigated. A comparative analysis and characterization of the program/erase (P/E) speed, retention and the process margin of cobalt NC memories including high-k and bandgap engineering technologies are performed by using the technology computer-aided design (TCAD) simulation. It is shown that NC memory with high-k dielectric (HfO2) has better performance in P/E speed and retention when the diameter of NC is below 5 nm. When the diameter is beyond 5 nm, on the other hand, the bandgap-engineered bottom oxide gate structure shows improved performance in P/E speed and retention. From the process margin perspective, as the permittivity of the dielectric gets larger, the limits of the diameter and the density of NCs allow the degree of freedom to become larger.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Nonvolatile memory with molecule-engineered tunneling barriers

We report a novel field-sensitive tunneling barrier by embedding C60 in SiO2 for nonvolatile memory applications. C60 is a better choice than ultrasmall nanocrystals due to its monodispersion. Moreover, C60 provides accessible energy levels to prompt resonant tunneling through SiO2 at high fields. However, this process is quenched at low fields due to highest occupied molecular orbital (HOMO)-lowest unoccupied molecular orbital (LUMO) gap and large charging energy of C60. Furthermore, we demonstrate an improvement of more than an order of magnitude in retention to program/erase time ratio for a metal nanocrystal memory. This shows promise of engineering tunnel dielectrics by integrating molecules in the future hybrid molecular-silicon electronics.

Modeling of retention characteristics for metal and semiconductor nanocrystal memories

Abstract The charge retention characteristics of metal nanocrystal (MNC) and semiconductor nanocrystal (SNC) memory devices are comparatively studied in this paper. A charge retention model is proposed, taking into account the quantum confinement effect, to account for the better retention characteristics of metal nanocrystal memory observed in the experiment. Simulation results are in good agreement with experimental data, which confirms the validity of this model. The impact of the nanocrystal size, tunneling dielectric materials (especially high-κ dielectrics), and tunneling dielectric thickness on the retention characteristics are all investigated for both the metal nanocrystals and the semiconductor nanocrystals.

Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal Based Nanotube/Nanowire Memories

The metal nanocrystal (NC)/carbon nanotube (CNT) based nonvolatile memory has been proposed recently in comparison to the microfabricated Si channel and Si NCs in ultranarrow channel structure. The electrostatics of metal NC-CNT devices during memory operations differ significantly from the metal NC memory with planar silicon channel. In this paper, we present the theoretical analysis on the three-dimensional (3-D) electrostatics of the NC-CNT device during memory operations, to illustrate the experimentally observed large number of charge storage at low gate bias (5 V) despite a 100-nm-thick bottom-gate control dielectric. NCs are electrostatically more strongly coupled to the two-dimensional (2-D) gate electrode than to the one-dimensional (1-D) channel, even when the NCs are in much closer proximity to the 1-D channel, for efficient tunneling and low-voltage program operation. Under the retention condition, the NC-CNT devices have lower electric field across tunneling oxide than that in the case of a 2-D channel. This increasing electric field difference with respect to program versus retention operations indicates larger ratio between program and retention times. Together with the large number of electrons stored per NC, this enhanced electrostatics can be utilized either to reduce the operating voltage or to reduce statistical fluctuation of the information storage

Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering

The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed

Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering

Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-K control and tunneling oxides. The high-K control oxide enables the effective-oxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-K tunneling oxide, on the other hand, improves the retention characteristics utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally, with the optimization strategies introduced in both parts I and II, a metal NC memory design with 1.0-V memory window, 13-mus programming, 2.5-mus erasing, and over 10-year retention time has been demonstrated at plusmn4V operation, which highlights the potential of NC memories as the next-generation nonvolatile memory

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.

Metal Nanocrystal Memory With High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Tunneling Barrier for Improved Data Retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.

Fabrication and characterization of a metal nanocrystal memory using molecular beam epitaxy

Recently, single and few electron devices have attracted a lot of attention due to their advantages when compared to the conventional DRAM or Flash memories. There is also a great effort to replace the silicon oxide (SiO2) with materials of high dielectric constant that could allow the further downscaling of MOSFET devices. In this work, initially we study the hafnium oxide (HfO2) deposition on thin SiO2. We fabricate a HfO2 layer, with good dielectric properties and with high dielectric constant. Then, we fabricate a novel MOS memory device with platinum (Pt) nanoparticles embedded in the HfO2/SiO2 interface.

Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technology

ABSTRACTExperimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit self-assembly process could be successfully adapted beyond 90nm metal nanocrystal memory technology with satisfactory parametric yield in the nanocrystal number density.

A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage

Based on the 2-bit-per-cell metal nanocrystal memories, a novel quad source/drain device capable of 4 bits per cell data storage is demonstrated. Along with the new device structure, a reliable parallel read scheme with low V/sub DS/ is also proposed and verified for 4-bit-per-cell operations. The proposed read scheme requires 1.125 read operations on average to read out the 4 bits stored in a cell, while minimizing the read disturb and interference between the different storage bits.

The Effect of Gate Geometry on the Charging Characteristics of Metal Nanocrystal Memories

ABSTRACTThis study presents the effect of gate geometry on the charging characteristics of metal nanocrystal memories. The effect is studied by varying the perimeter to area ratio, number of convex corners and concave corners of the gate of a metal-oxide-semiconductor (MOS) capacitor with embedded gold nanocrystals. It can be observed that the nanocrystal charging rate increases for a smaller perimeter to area ratio. The presence of concave and convex corners increases the nanocrystal charging rate. Based on this study it is expected that gate geometries with low perimeter to area ratio and with selected convex and concave corners would increase the nanocrystal charging rate.

Metal nanocrystal memories. I. Device design and fabrication

This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices.

Metal nanocrystal memories-part II: electrical characteristics

This paper describes the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime have been investigated and compared with Si nanocrystal memory devices. With hot-carrier injection such as the programming mechanism, retention time up to 10/sup 6/ s has been observed and 2-bit-per-cell storage capability has been demonstrated and analyzed. The concern of the possible metal contamination is also addressed by current-voltage (I-V) and capacitance-voltage (C-V) characterizations. The extracted inversion layer mobility and minority carrier lifetime suggest that the substrate is free from metal contamination with continuous operations.