Abstract

Based on the 2-bit-per-cell metal nanocrystal memories, a novel quad source/drain device capable of 4 bits per cell data storage is demonstrated. Along with the new device structure, a reliable parallel read scheme with low V/sub DS/ is also proposed and verified for 4-bit-per-cell operations. The proposed read scheme requires 1.125 read operations on average to read out the 4 bits stored in a cell, while minimizing the read disturb and interference between the different storage bits.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call