Metal Gate Research Articles

Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications

In this study, the influence of AlN barrier thickness (tb) on the RF & DC performances of 50 nm recessed T-gate Fe-doped AlN/GaN/SiC HEMT is investigated. The proposed HEMT incorporates a graded back-barrier (GBB) feature that raises the conduction band (CB) discontinuity at GaN/AlGaN junction to increase carrier confinement. With excellent electron confinement, the electrical characteristics for a 6 nm AlN barrier thickness show the highest transconductance of 468.9 mS/mm, a maximum ID of 1.546 A/mm, and a peak fT of 355 GHz at VDS = 2.5 V due to better epitaxial quality, and a reduction in parasitic channel generation due to GBB. When tb increases, the Vth decreases or becomes more negative i.e., moves left, which causes the ID to fall and degrades performance. This study also examines the influence of gate metals on the electrical performance of the proposed HEMT. According to the TCAD results, Pt-gate HEMTs had better RF performance. Furthermore, the simulation performed to examine the effects of scaling source-drain spacing (LSD) showed that the key to improving RF/DC performance is to reduce gate-to-drain and gate-to-source distances. It has been observed that the electron velocity of the HEMT is significantly influenced by the barrier thickness, LGS, and LGD. It comes as no surprise that this technology will be at the frontlines of future RF power applications.

A compact model of DC I–V characteristics for depleted Ga2O3 MOSFETs

In this article, we present a novel behavioral compact model based on the hyperbolic tangent function that accurately reproduces the DC current-voltage (I–V) characteristics of the depleted Ga2O3 MOSFET. The proposed model fully explores and accounts for the effects of the spacing between the n+ region and the gate metal, as well as the gate-length scaling on the static electric properties of Ga2O3 MOSFETs. We demonstrate the effectiveness of our model by matching the I–V curves obtained from simulations and experiments, and good agreements are achieved by appropriately adjusting the fitting parameters. In addition, we compare the calculated transconductance and output conductance with the numerically simulated results and observe good agreements. The proposed model is expected to be a valuable tool for circuit design involving depleted Ga2O3 MOSFETs. It provides a more accurate and efficient means of simulating the behavior of these devices, which can aid in the development of new and innovative circuit designs. Overall, our model represents a significant contribution to the field of Ga2O3 MOSFET research and has the potential to facilitate the continued advancement and optimization of this technology.

Optimizing the initial weights of a PID neural network controller for voltage stabilization of microgrids using a PEO-GA algorithm

This paper proposes an adaptive PID neural network (PIDNN) controller for direct and quadrature voltage control of three-phase inverters for islanded microgrids. A hybrid metaheuristic optimization algorithm is proposed for the initial weight selection of the proposed PIDNN controller using a discrete-time simulation model incorporating the nonlinearity of the insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) switches of the inverter. The proposed hybrid optimization (HO) approach is a combination of population extremal optimization (PEO) and genetic algorithm (GA). It turned out that the proposed HO-PIDNN control scheme excelled the PEO, GA, and particle swarm optimization-based PIDNN controllers in terms of the objective function value, which is composed of the integral time absolute tracking error of the output voltage and a chattering penalty factor. Also, the control system outperformed the model reference adaptive PID control technique from the literature.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

Metal-Induced Trap States: The Roles of Interface and Border Traps in HfO2/InGaAs.

By combining capacitance-voltage measurements, TCAD simulations, and X-ray photoelectron spectroscopy, the impact of the work function of the gate metals Ti, Mo, Pd, and Ni on the defects in bulk HfO2 and at the HfO2/InGaAs interfaces are studied. The oxidation at Ti/HfO2 is found to create the highest density of interface and border traps, while a stable interface at the Mo/HfO2 interface leads to the smallest density of traps in our sample. The extracted values of Dit of 1.27 × 1011 eV-1cm-2 for acceptor-like traps and 3.81 × 1011 eV-1cm-2 for donor-like traps are the lowest reported to date. The density and lifetimes of border traps in HfO2 are examined using the Heiman function and strongly affect the hysteresis of capacitance-voltage curves. The results help systematically guide the choice of gate metal for InGaAs.

Effect of Different pH in HKMG on the Selection Ratio of Al and Poly Removal Rates

When the characteristic size of integrated circuits developed to 28 nm and below according to Moore’s Law, aluminum was widely used as a gate material in HKMG structures, and the CMP technology of aluminum gates was a breakthrough in the upgrading of HKMG post-gate process technology. Aluminum gate CMP requirements are much higher than aluminum wiring and Damascus wiring, the key to aluminum gate CMP is to achieve high material removal selectivity and high perfect surface. At home and abroad, the research on aluminum gate CMP is mostly concentrated on removal rate and Al–Co galvanic corrosion. This paper will explore the influence of the rate selection ratio of aluminum and polysilicon under glycine hydrogen peroxide system with different pH conditions via CMP experiments, electrochemical experiments, UV and XPS spectroscopy experiments, etc.

Design and analysis of Z shaped InGa0.5As0.5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application

—In this paper, a high-k stacked gate Z shaped hetero-juncture TFET (Z-HTFET) is introduced as transducer sensor for the application of hydrogen gas detection. The positioning of stacked gate over the entire source region resulting Z shaped TFET exhibits vertical line tunneling mechanism between the source and the channel yielding higher ON state current (Id) as compared to conventional double gate (DG) TFET. Further, the combination of low band gap source of In0.5Ga0.5As and hetero-gate dielectric engineering helps to facilitate improved device current, steeper subthreshold slope and lower leakage current (Ileak) conduction. Here, palladium (Pd) and the high-k gate stack (HfO2/SiO2) is used as the sensing platform. The induced shift in work function of Pd gate electrode due to the dissociation and diffusion of hydrogen gas molecules into the catalytic gate metal is considered as the detection metric for calculating the sensitivity of the proposed TFET based gas sensor. The behavior of the hydrogen gas sensor is studied using numerical device simulator in terms of surface potential, electric field, transfer characteristics, transconductance, Id/Ileak ratio with variation in work-function and finally Id/Ileak sensitivity is measured. The sensor behavior for a wide range of temperature is also examined to explore the temperature stability of the device. The comparative performance analysis of Z-HTFET with sensitivity of 95.26% establishes the superiority of the device for hydrogen gas sensing as compared to some of the recently reported FET based sensors.

Temperature dependent characteristics of β -Ga2O3 FinFETs by MacEtch

Understanding the thermal stability and degradation mechanism of β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial for their high-power electronics applications. This work examines the high temperature performance of the junctionless lateral β-Ga2O3 FinFET grown on a native β-Ga2O3 substrate, fabricated by metal-assisted chemical etching with Al2O3 gate oxide and Ti/Au gate metal. The thermal exposure effect on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and specific on-resistance (Ron,sp), as a function of temperature up to 298 °C, is measured and analyzed. SS and Ron,sp increased with increasing temperatures, similar to the planar MOSFETs, while a more severe negative shift of Vth was observed for the high aspect-ratio FinFETs here. Despite employing a much thicker epilayer (∼2 μm) for the channel, the high temperature performance of Ion/Ioff ratios and SS of the FinFET in this work remains comparable to that of the planar β-Ga2O3 MOSFETs reported using epilayers ∼10–30× thinner. This work paves the way for further investigation into the stability and promise of β-Ga2O3 FinFETs compared to their planar counterparts.

Importance of temperature dependence of interface traps in high-k metal gate stacks for silicon spin-qubit development

While semiconductor-based spin qubits have demonstrated promising fidelities exceeding 99.9%, their coherence time is limited by the presence of charge noise. However, fast process optimization for reduced charge noise becomes challenging due to the time-consuming nature of cryogenic measurements. Hence, this work explores low frequency analysis methods to determine interface trap densities, their temperature dependence, and correlation with observed noise levels. The herein presented results provide evidence for strong temperature dependence of the interface trap density. Moreover, good agreement is observed between charge pumping and conductance-based methods. Finally, differences in temperature dependent trends of flicker noise are observed, indicating additional influences, which need to be considered for further device optimization.

Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

A label-free dielectric-modulated biosensor using SiGe-heterojunction dual cavity dual metal electrically doped TFET

The detection of biomolecules has been accomplished in this article by using the tunnel field effect transistor’s (TFET) bipolar nature. The fabrication procedure has been made simpler, the prices have gone down, and random dopant fluctuation (RDFs) have been eliminated using the charge plasma concept. The objective of this work is to investigate the performance of a DopingLess- Dual Metal Gate- Dual Cavity- HeteroJunction- Tunnel Field Effect Transistor (DL-DMG-DC-HJ-TFET) biosensor that can sense biomolecules in both the ON and ambipolar states. It is feasible to recognize many types of biomolecules concurrently by taking into account the cavities at both tunneling junctions. The suggested biosensor’s OFF state current has been reduced and its sensitivity has been increased via the use of gate workfunction engineering and bandgap engineering. It has been investigated how the presence of proteins in the cavities affects electrical properties such as energy band diagram (EBD), surface potential (SP), subthreshold Swing (SS), threshold voltage , and current ratio The impact of temperature, germanium mole fraction, and position of biomolecules is also analyzed in this work. A comparative analysis for drain current sensitivity is presented considering different previous works.

First Demonstration of Vertical Sandwich GAA TFETs with Self-Aligned High-k Metal Gates and Abrupt Doping Tunneling Junctions

A new type of vertical sandwich gate-all around tunneling field-effect-transistors (TFETs), called VSATFETs, was demonstrated firstly with a CMOS-compatible process. The VSATFETs with self-aligned high-κ metal gates (HKMG) and abrupt doping tunneling junctions were fabricated with the epitaxial of p+−Si/i-SiGe/n+−Si sandwich structure and an isotropic quasi-atomic layer-etch (qALE) process. VSATFETs have the advantage of excellent control of channel size, because its gate-length is mainly determined by the thickness of SiGe film grown by epitaxy, and the diameter of the nanowires (NWs)/thickness of nanosheets (NSs) is determined by the qALE etching of SiGe selective to Si. A NW VSATFET with a diameter of 18 nm was fabricated and exhibits excellent characteristics: SSmin = 61.64 mV dec−1, Ion = 2.25 × 10−7 A u−1m−1 (@Vgs−Vt = 0.45 V, Vd = 0.65 V), Ion/Ioff = 1.81 × 106, DIBL = 7.58 mV. The effect of interface traps on the device performance was analyzed by the calibrated model. It is found that the device performance can be improved by decreasing the thickness/diameter of NS/NW TFET.

Modelling and simulation of organic (Pentacene) field effect transistor

In this paper, we studied the simulation of the electrical parameters of an organic pentacene field-effect transistor (OFET) based on the Poole-Frenkel method, which aims to provide a better balance between static and dynamic performance parameters. This approach gives us a quick and easy way to model devices with strong nonlinear behaviour without going into the physics of the device. Metal gates, room temperature deposited gate dielectric, and vacuum deposited pentacene as a semiconductor are used in an inverted (bottom gate, top contact) and planar (bottom gate, bottom contact) device structure. The OFETs possess a channel length of 2 μm as well as a channel width of 10 mm. The Silvaco 2-D Atlas simulator is usedas the tool for finite element simulation. According to the simulation results, the planner structure's source electrode can deliver more current than the staggered structure. The contact resistance of the bottom contact structure (3.973×104Ω) was also found to be higher than that of the top contact structure (2.386×104Ω), which limits the mobility of the charge carriers within the semiconductor and, as a result, lowers the drain-source current.

Plasmons in a Strip with an Anisotropic Two-Dimensional Electron Gas Fully Screened by a Metal Gate

Plasmons in a Strip with an Anisotropic Two-Dimensional Electron Gas Fully Screened by a Metal Gate

Minority carrier diffusion length in interface-confined PbS colloidal quantum dot (CQD): Effect of CQD surface modification on diffusion length in ultrathin PbS CQD films

Photocurrent microscopy (PCM) is a versatile tool for probing charge carrier transport associated with energy band bending at an interface. For the first time, we report the ligand-dependent electronic properties of interface-confined colloidal quantum dots (CQDs) near a metal electrode and gate dielectric layers using ultrathin lead sulfide (PbS) CQD films embedded in field effect transistors (FETs). We have compared the minority carrier (electron) diffusion length (MCDL) of ultrathin PbS CQD films treated with 1,2-ethanedithiol (EDT) and ammonium sulfide ((NH4)2S) using a bottom-contact FET structure in combination with PCM. We found that the MCDL was greater in the EDT-treated PbS CQDs than in the (NH4)2S-treated PbS CQDs. The MCDL at the 2D carrier accumulation layer was observed to depend on the concentration of the majority carrier (hole). During effective electrical channel formation by electrical gating, the MCDL decreased with hole accumulation (decreasing gate voltage) in the p-channel (NH4)2S-treated PbS CQD FET, whereas it remained similar in the EDT-treated PbS CQD FET. The effect of the majority carrier concentration on the MCDL was more pronounced in the (NH4)2S-treated sample than in the EDT-treated sample. The difference in the MCDL is attributed to a difference in the surface trap density caused by different ligand treatments.

Compact Modeling of Process Variations in Nanosheet Complementary FET (CFET) and Circuit Performance Predictions

In this work, a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER). Different from the conventional NS GAA FET, GER has a significantly different impact on NS GAA CFET, due to the additional p-type work-function (p-WF) liner for p-FET threshold voltage tuning as well as the common metal gate, and a negative correlation with p-WF thickness is introduced into GER model. The proposed model is embedded into Berkeley short-channel insulated-gate field-effect transistor model-common multi-gate (BSIM-CMG) to predict the device performance variability by HSPICE Monte Carlo (MC) simulations. Excellent agreement between stochastic TCAD and HSPICE MC simulations is demonstrated. The effect of process variations on the power-performance-area (PPA) of standard cells (SDCs) and ring oscillator (RO) circuit is predicted by the proposed model. Most of the process variations make a more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 20% change in power consumption in NOR2. WFV has the greatest impact on RO PPA, making a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 12.3% change in power consumption. The proposed model provides a helpful guideline for the random variation-aware CFET circuit design and related technology process development.

Thermostimulated luminescence analysis of oxygen vacancies in HfO[formula omitted] nanoparticles

Hafnia has already been established in CMOS technologies as a high-k metal gate material, however, recently it has also become a promising material in ferroelectric applications. In this study we have investigated intrinsic defects such as oxygen vacancies in undoped and 5at%Eu HfO2 synthesized by sol-gel, combustion, auto-ignition combustion, hydrothermal and precipitation methods. All samples were of monoclinic phase with crystallite sizes of 16–40 nm. Photoluminescence (PL), thermostimulated luminescence (TSL) both below and above room temperature as well as XRD and TEM methods were used to identify potential VO3+1, VO3+2, VO4+1 and VO4+2 defects. Activation energies were determined for the oxygen vacancies and grain boundary effects were studied. Both PL and TSL wavelength peak spectra shift to higher energies with the increase of temperature was observed.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability (NBTI) can be attributed to three mutually uncoupled physical mechanisms, i.e., the generation of interface traps (ΔV IT), hole trapping in pre-existing gate oxide defects (ΔV HT), and the generation of gate oxide defects (ΔV OT). In this work, the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate (HKMG) process is thoroughly studied. The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature. The effects of the three underlying subcomponents are evaluated by using the comprehensive models. It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress. Moreover, the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted. The dependence of operating lifetime on stress bias and temperature is also discussed. It is observed that NBTI lifetime significantly decreases as the stress increases. Furthermore, the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

Performance Improvement Induced by Metal Gate Undercut for Ring Oscillator

The performance of 101-stage ring oscillator is effectively improved by the undercut process of metal gate for 28 nm high-k first metal gate-last planar CMOS technology. Using a simple over-etch process after dummy poly-Si gate formation, the undercut metal gate can be fabricated. The metal gate undercut is demonstrated to be able to effectively reduce the overlap capacitance between gate and drain, which further results in over 3.7% improvement of the maximum oscillating frequency at the same integrated circuit active current. While the comparable alternating current performance with reduced power consumption can be obtained.

40‐3: Distinguished Paper: Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

This paper presents recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. Experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. Process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction of improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs, as well as gain more physical insight in the bottom‐gate LTPS device configuration, to enable reliable low‐power high‐performance AMOLED display applications.