Metal Gate Research Articles

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

Ultrahigh-responsivity waveguide-coupled optical power monitor for Si photonic circuits operating at near-infrared wavelengths

A phototransistor is a promising candidate as an optical power monitor in Si photonic circuits since the internal gain of photocurrent enables high responsivity. However, state-of-the-art waveguide-coupled phototransistors suffer from a responsivity of lower than 103 A/W, which is insufficient for detecting very low power light. Here, we present a waveguide-coupled phototransistor operating at a 1.3 μm wavelength, which consists of an InGaAs ultrathin channel on a Si waveguide working as a gate electrode to increase the responsivity. The Si waveguide gate underneath the InGaAs ultrathin channel enables the effective control of transistor current without optical absorption by the gate metal. As a result, our phototransistor achieved the highest responsivity of approximately 106 A/W among the waveguide-coupled phototransistors, allowing us to detect light of 621 fW propagating in the Si waveguide. The high responsivity and the reasonable response time of approximately 100 μs make our phototransistor promising as an effective optical power monitor in Si photonic circuits.

Comparative Performance Analysis of the DC-AC Converter Control System Based on Linear Robust or Nonlinear PCH Controllers and Reinforcement Learning Agent

Starting from the general topology and the main elements that connect a microgrid represented by a DC power source to the main grid, this article presents the performance of the control system of a DC-AC converter. The main elements of this topology are the voltage source inverter represented by a DC-AC converter and the network filters. The active Insulated Gate Bipolar Transistor (IGBT) or Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) elements of the DC-AC converter are controlled by robust linear or nonlinear Port Controlled Hamiltonian (PCH) controllers. The outputs of these controllers are modulation indices which are inputs to a Pulse-Width Modulation (PWM) system that provides the switching signals for the active elements of the DC-AC converter. The purpose of the DC-AC converter control system is to maintain ud and uq voltages to the prescribed reference values where there is a variation of the three-phase load, which may be of balanced/unbalanced or nonlinear type. The controllers are classic PI, robust or nonlinear PCH, and their performance is improved by the use of a properly trained Reinforcement Learning-Twin Delayed Deep Deterministic Policy Gradient (RL-TD3) agent. The performance of the DC-AC converter control systems is compared using performance indices such as steady-state error, error ripple and Total Harmonic Distortion (THD) current value. Numerical simulations are performed in Matlab/Simulink and conclude the superior performance of the nonlinear PCH controller and the improvement of the performance of each controller presented by using an RL-TD3 agent, which provides correction signals to improve the performance of the DC-AC converter control systems when it is properly trained.

Vertical GaN/InGaN/GaN heterostructure tunnel field-effect transistor: DC and analog/RF performance

This work reports an [Formula: see text]-type GaN/InGaN/GaN heterostructure vertical double-gate tunnel field-effect transistor (VTFET) using exhaustive calibrated simulation for the first time. Investigation has been done for the proposed structure by including a polarization layer of InGaN near the source-channel junction. From the analysis, it has been observed that after the introduction of polarization layer near the source-channel interface, drain current increases due to the increase in charge concentration (2DEG) near the interface due to inter-band tunneling. Value of 2DEG concentration achieved post introducing the polarization layer is [Formula: see text] [Formula: see text]. The reported structure is optimized using parametric sweep optimization technique. Here, a detailed dc and analog/RF performance estimation has been done for the structure with heterostructure. In-depth sensitivity analysis has been done for the structure with the polarization layer. It is reported that the structure with HfO2 as the dielectric material with [Formula: see text] of 2 nm and with gate metal work function of 5.8 eV gives the optimum performance at 300 K. Further, it demonstrates high cutoff frequency ([Formula: see text] and gain bandwidth product (GBW) as 1000 GHz and 300 GHz, respectively. Hence, the reported structure is a better alternative for high-power steep switching analog and RF applications.

Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact

An on-chip digital sensor has been demonstrated in 28nm High-k Metal Gate (HKMG) for bias temperature instability (BTI) statistical characterization with the benefits: fast statistical measurement, less recovery impact (Toff-stress@around 15ns, Fast Period Sampling (FPS) @around 300ns), and high resolution (0.1mV of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula> Vth). As far as we know, it is the first time to statistically observe the very early stage of trap recovery of individual device in practical scenario, e.g., static random-access memory (SRAM). We find that three Negative BTI (NBTI) recovery behaviors, 2/3/4-step with clear transition slope, co-exist in HKMG devices. Our further analysis ascribes the phenomena to co-existing of four types of defects in 28nm HKMG Devices Under Test (DUTs). Three types are recoverable and one unrecoverable. The transition slope instead of steep drop between steps is the aggregative effects of one certain type of recoverable defect contained across DUTs. More types of defects lead to more Vth shift. But the contribution percentage of unrecoverable defect remains quite close, while recoverable defects dominate the Vth degradation. Only when the Toff-stress is less than the starting point of 1st recover step (within 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> in our case), accurate and consistent Vth degradation data can be achieved.

FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

Spin transfer torque (STT) magneto-resistive random access memory (MRAM)-based non-volatile logic circuits require asymmetric write current to enable high efficiency. This requires methods at the device or circuit level to meet the asymmetric current requirement of STT MRAM-based circuits. In this work, we propose a novel asymmetric fin field-effect transistor (FinFET)-based access device, along with a process flow, at a 3-nm node. The proposed device uses selective fin-trimming during the replacement metal gate (RMG) process, along with a dielectric deposition in the trimmed fin regions. This process does not require a new mask design and can be easily integrated into standard CMOS technology, and thus is very attractive with respect to previously proposed devices. With 3-D TCAD modeling, we show that up to 26% asymmetricity can be achieved with this device architecture, which meets the requirement of STT MRAM-based circuits. The proposed device offers 30% lower gate capacitance with respect to previously proposed devices.

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8}\times {8}$ </tex-math></inline-formula> segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} ^{{4}}$ </tex-math></inline-formula> seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.

Theoretical Study of Electronic Transport in Two-Dimensional Transition Metal Dichalcogenides: Effects of the Dielectric Environment

We discuss the effect of the dielectric environment (substrate/bottom oxide, gate insulator, and metal gates) on electronic transport in two-dimensional (2D) transition metal dichalcogenides (TMD) monolayers. We employ well-known ab initio methods to calculate the low-field carrier mobility in free-standing layers and use the dielectric continuum approximation to extend our study to layers in double-gate structures, including the effects of dielectric screening of the electron-phonon interaction caused by the bottom oxide and the gate insulator, and of scattering with hybrid interface optical-phonon/plasmon excitations (``remote phonon scattering''). We find that the presence of insulators with a high dielectric constant may improve significantly the carrier mobility. However, scattering with the interface hybrid excitations negates this gain and degrades the mobility significantly below its free-standing value. We find that this process is dominated by long-wavelength interactions that, for the carrier sheet density of interest, are strongly affected by the coupling with the 2D plasmons. Considering 2D layers in a double-gate geometry with ${\mathrm{Si}\mathrm{O}}_{2}$ as bottom oxide and various top-gate insulators, we find that the mobility decreases as the top-insulator dielectric constant increases (from hBN to ${\mathrm{Zr}\mathrm{O}}_{2}$), as expected. However, we observe two main deviations from this trend: high mobility is predicted in the case of the weakly polar hBN, and much lower than expected mobility is calculated in the case of gate-insulator/TMD/bottom-oxide stacks in which two or more polar materials have optical phonons with similar resonating frequencies. We also find that the effect of screening by metal gates is noticeable but not particularly strong. Finally, we discuss the effect of the TMD dielectric constant, of the free-carrier density, and of temperature on the transport properties of TMD monolayers.

DC/RF performance and temperature sensitivity of ground-plane based JLTFET

ABSTRACT This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high- gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage (), and ratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here.

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Reliability, Applications and Challenges of GaN HEMT Technology for Modern Power Devices: A Review

A new generation of high-efficiency power devices is being developed using wide bandgap (WBG) semiconductors, like GaN and SiC, which are emerging as attractive alternatives to silicon. The recent interest in GaN has been piqued by its excellent material characteristics, including its high critical electric field, high saturation velocity, high electron mobility, and outstanding thermal stability. Therefore, the superior performance is represented by GaN-based high electron mobility transistor (HEMT) devices. They can perform at higher currents, voltages, temperatures, and frequencies, making them suitable devices for the next generation of high-efficiency power converter applications, including electric vehicles, phone chargers, renewable energy, and data centers. Thus, this review article will provide a basic overview of the various technological and scientific elements of the current GaN HEMTs technology. First, the present advancements in the GaN market and its primary application areas are briefly summarized. After that, the GaN is compared with other devices, and the GaN HEMT device’s operational material properties with different heterostructures are discussed. Then, the normally-off GaN HEMT technology with their different types are considered, especially on the recessed gate metal insulator semiconductor high electron mobility transistor (MISHEMT) and p-GaN. Hereafter, this review also discusses the reliability concerns of the GaN HEMT which are caused by trap effects like a drain, gate lag, and current collapse with numerous types of degradation. Eventually, the breakdown voltage of the GaN HEMT with some challenges has been studied.

A Harmonic Radar Tag With High Detection Range Utilizing Ge FinFETs CMOS Technology

This study fabricated and verified a germanium (Ge) fin field-effect transistor (FinFET) on developed GeSOI platform. The Ge FinFETs were demonstrated for radio-frequency (RF) applications with a harmonic radar tag. The relation between the detection range (Rd), received power (Pr), and threshold voltage (Vth) of a diode was qualitatively discussed. To meet the requirement of a low Vth, two kinds of Ge FinFETs with different metal gates were fabricated and compared. After the evaluation of electrical characteristics of n-type and p-type Ge FinFETs with different fin numbers, a tag for harmonic radar was designed by integrating diode-connected TiN gate 1-fin Ge FinFETs (Vth = 0.1 V) with a high impedance antenna. The RF performance was evaluated at 9.4 GHz and 18.8 GHz. The results indicated a 50 % improvement in the Rd as compared to the tag using a commercial Schottky diode. Therefore, the proposed low-Vth Ge FinFET on developed GeSOI platform for complementary metal–oxide–semiconductor (CMOS) is promising for high-sensitivity harmonic radar applications.

Hybrid GaO/AlGaN/GaN Ultraviolet Detector With Gate Metal in the Grooved AlGaN Layer for Obtaining Low Dark Current and Large Detectivity

In this work, a metal/Ga2O3/AlGaN/GaN hybrid-structured metal–semiconductor–metal ultraviolet photodetector (MSM UV PD) with low dark current has been proposed and fabricated. In the dark condition, the depletion region formed by the metal gate and the AlGaN layer pinches off the two-dimensional electron gas (2DEG) channel, and we can obtain a dark current even lower than 10−10 A/cm2. In the illumination condition, due to the electric field formed by the metal and the Ga2O3 layer, the photogenerated electrons will move to the AlGaN/GaN channel to form the 2DEG. We then get a photo-to-dark current ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.77\times10$ </tex-math></inline-formula> 8. Furthermore, the detectivity of the device is higher than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.30\times10$ </tex-math></inline-formula> 12 Jones when a 254-nm UV illumination signal is applied.

Charge filling induced quasi-two dimensional charge/spin density wave channel in a ballistic transport device

Charge filling controlled mean field metal–insulator phase transition is examined in the context of two dimensional Fermi surface nesting and van Hove singularity induced charge density wave (CDW), spin density wave (SDW) condensates. In the framework of a coherent ballistic transport model utilizing the Non-Equilibrium Green Function approach (NEGF), a three terminal device with metallic gate, source, drain and CDW/SDW channel is simulated and studied. Within the validity of mean field approximation, we exposit the commensurability and boundary effects. The efficacy of the Hubbard model for (quasi) two dimensional Charge and Spin Density Wave materials is discussed. A two orbital generalization of the effective Hamiltonian is proposed for transport calculations in rare earth Tellurides RTe 3.

Performance Study of DM-DG-OS JL-MOSFET based Biosensor in Detecting Charged Nanometric Biospecies

In this paper, for the first time, a dual-metal double-gate with oxide stack (low-k/high-k) junctionless MOSFET (DM-DG-OS JL-MOSFET) based sensor device has been explored for finding its suitability in detecting charged nanometric biospecies under dry environment condition. The analysis of sensing performance of the device for such detection is made in terms of the absolute and the relative changes in threshold voltage (Vth). The influence of work-function difference of dual metal gate electrodes, along with the position of nanogap cavity, on the sensing metrics has been thoroughly investigated. The impact of the cavity dimensions on sensitivity parameters of the projected device is also studied. An optimum cavity dimension, for channel length (Lch) of 1 µm, is found to be 400 nm × 10 nm in yielding measurable sensitivity parameters for charged nanometric biospecies detection. A device with 1-µm Lch exhibits superior sensitivity performance in terms of percentage improvements in the absolute and the relative changes in Vth for a higher drain-side gate-metal work-function (ϕM2) relative to source-side gate-metal work-function (ϕM1) for source-side cavity (400 nm × 10 nm) compared to the case when ϕM1>ϕM2 and the cavity is located near drain-side. Respective performance enhancements are found to be 30.7% and 74% for detection of negatively charged nanometric biospecies. The sensor devices with Lch of 50 nm show the similar trend.

(Digital Presentation) Negative Bias Illumination Stress on a-Igzo TFT with a Top Barrier

The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can improve not only the electrical properties and the positive bias temperature instability as compared to the single-layer TFT (SL-TFTs) [1][2] but also the negative bias illumination stress (NBIS). In this work, DL-TFTs have less negative VT shifts than that of SL-TFTs under NBIS. Moreover, the negative VT shift of DL-TFTs decreases with increasing top barrier thickness due to the energy barrier formed by the valence band discontinuity at the interface between the channel layer and the top barrier. Experimental Process: The 100 nm Mo/Al layers were first deposited on a glass substrate and patterned to form the bottom gate (BG) metal, followed by the deposition of 320 nm thick SiNx/SiOx gate insulator (GI) using plasma-enhanced chemical vapor deposition (PECVD). For the active layer of SL-TFT, 15 nm a-IGZO with high indium content was deposited to form a high mobility channel (HM-IGZO) using radio frequency magnetron sputtering with Ar plasma. As for the DL-TFTs, an extra standard a-IGZO (STD-IGZO, the atomic composition of the target is In2O3:Ga2O3:ZnO=1:1:2 mol%) was deposited as a top barrier. Two different top barrier thicknesses were deposited (10 nm and 30 nm) to investigate the thickness effect on the NBIS. The active layer was then patterned by photolithography. A 260 nm Ti was deposited and patterned by photolithography and reactive ion etch (RIE) as the S/D metal, followed by SiOx/SiNx top gate insulator deposition and the transparent indium tin oxide (ITO) top gate (TG) metal formation. To conduct the NBIS test, -30 V and 0 V were applied to the bottom gate and the top gate, respectively, and a light source with a wavelength of 365 nm was used as the illumination stress. Additional 100 nm films of HM and STD IGZO were deposited to investigate the band alignment. The bandgap (Eg), valence band offsets (EF-EV, where EF is the Fermi level and EV is the valence band edge), and work function can be extracted by Tauc method, X-Ray photoelectron spectroscopy (XPS), and Kelvin probe force microscopy (KPFM), respectively, to obtain the band alignment of the HM (channel layer) and the STD (top barrier) IGZO [3]. Results and Discussions: The evolution of VT shifts under NBIS are shown in Fig. 1. DL-TFTs have less VT shift than that of SL-TFT. Since the energy of the photon (3.4 eV) is larger than the bandgap of the a-IGZO (~3 eV), electron-hole pairs are generated by the light source. Since a negative voltage is applied to the BG, the generated holes are trapped into the BG GI, resulting in the negative VT shift. In DL-TFTs, the holes generated in the top barrier cannot be trapped into the BG GI due to the energy barrier formed by the valence band discontinuity. With the band alignment analysis [1], the valence band discontinuity is found to be 0.39 eV, which is high enough to stop the holes generated in the top barrier from trapping into the BG GI. The electrons generated in the top barrier can still be trapped into the TG GI, compensating the negative VT shift (Fig. 2(a)), resulting in a smaller VT shift in DL-TFTs than that of SL-TFTs. Reportedly, the VT shift increases with increasing a-IGZO thickness in SL-TFTs [4]. However, the VT shift decreases with increasing top barrier thickness in DL-TFTs (Fig. 1). Although the generated electron-hole pairs in the top barrier increase with increasing top barrier thickness, the additional holes cannot be trapped into the BG GI due to the valence band discontinuity, while the additional electrons can easily be trapped into the TG GI, leading to more VT shift compensation and thus less negative VT shift in the DL-TFT (Fig. 2(b)). Conclusion: The DL-TFTs have less VT shift under NBIS as compared to SL-TFTs. The NBIS can be further improved by increasing the top barrier thickness. Acknowledgment: This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 110-2218-E-A49-013-MBK, Grant MOST 110-2218-E-002-030, and Grant MOST 110-2622-8-002-014, and in part by the Ministry of Education, Taiwan, under Grant NTU-CC-110L892601. Reference: [1] J.-C. Chiu et al., J-EDS (2021) [2] J.-C. Chiu et al., IEDMS (2021) [3] A.-H. Tai et al., TED (2019) [4] M. M. Billah et al., EDL (2016) Figure 1

Challenges for Sige Bicmos in Advanced-Node SOI

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution.The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs.Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work.Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed.The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics.Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm.The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects.The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work.This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.[1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

(Invited, Digital Presentation) Low Voltage Operation of CMOS Inverter Based on WSe2 n/p FETs

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs.For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively.Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts.Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V.Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits.

Impact on performance of dual stack hetero- gated dielectric modulated TFET biosensor due to Si1-xGex pocket variation

In this work, the performance evaluation of a dual stack hetero-gated pocket modulated tunnel FET (DSHGPM-TFET) based biosensor is presented. In the proposed device, cavity is formed by etching a portion of gate metal on both side of channel. The device contains a Si1-xGex pocket buried in the source region, where x (Ge mole fraction) is varied and effect on ION, VTH, and SS sensitivity is analyzed. The effect of x (=0, 0.4, 0.8, 1) and k (= 1, 5, 7, 10, 12) variation in DSHGPM-TFET is compared and noted. Also, the subthreshold swing (SS) and ION/IOFF ratio vs. dielectric constant at different x are plotted. Sensitivity is observed in the presence of neutral and charged (positive/negative) biomolecules within the cavity. Results show that increasing x of the pocket as well as k, enhances the sensitivity parameters. It is seen that sensitivity increases (decreases) with positive (negative) charged biomolecules. The work is further extended to study the performance of biosensor in non-ideal conditions. The effect of steric hindrance is studied by employing four different step profiles in cavity-concave, convex, decreasing, and increasing for two fill-factor (FF) 40% and 61%. The dynamic range of the proposed biosensor is estimated by varying x. Finally, the proposed sensor is compared with other biosensors existing in literature.