FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

Abstract

Spin transfer torque (STT) magneto-resistive random access memory (MRAM)-based non-volatile logic circuits require asymmetric write current to enable high efficiency. This requires methods at the device or circuit level to meet the asymmetric current requirement of STT MRAM-based circuits. In this work, we propose a novel asymmetric fin field-effect transistor (FinFET)-based access device, along with a process flow, at a 3-nm node. The proposed device uses selective fin-trimming during the replacement metal gate (RMG) process, along with a dielectric deposition in the trimmed fin regions. This process does not require a new mask design and can be easily integrated into standard CMOS technology, and thus is very attractive with respect to previously proposed devices. With 3-D TCAD modeling, we show that up to 26% asymmetricity can be achieved with this device architecture, which meets the requirement of STT MRAM-based circuits. The proposed device offers 30% lower gate capacitance with respect to previously proposed devices.