Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS

Abstract

The spin transfer torque (STT) magneto-resistive random access memory (MRAM) often uses bulk and silicon on insulator (SOI) metal oxide semiconductor (NMOS) as access device. However, the drive current reduction due to the substrate bias effect in bulk NMOS and lattice heating effect in silicon on insulator (SOI) NMOS makes them less suitable for STT MRAMs. The reduction in write current actually increases the write errors in STT MRAMs that adversely affects the reliability of STT MRAM cell. Taking these reliability concerns into account, an STT MRAM cell with fully depleted (FD) silicon carbide (4H-SIC) substrate NMOS is presented that is impervious to drive current reduction due to the substrate bias and self heating effects. The proposed STT MRAM cell with FDSIC NMOS exhibits a maximum variation of 3% in the steady state lattice temperature manifesting very low possibility of thermal fatigue and device failures. Moreover, the proposed cell offers extremely low leakage power dissipation that is almost three orders smaller than the conventional cell. The circuit level analysis of STT MRAM is done using calibrated Verilog-A models. Encouragingly, the proposed FDSIC cell demonstrates 45% improvement in write error rate over conventional FDSOI cell.