Metal Gate Structure Research Articles

Investigations of 4H‐SiC trench MOSFET with integrated high‐K deep trench and gate dielectric

AbstractThis paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit.

Simulation Study of Dual Metal-Gate Inverted T-Shaped TFET for Label-Free Biosensing

In this article, an inverted T-shaped tunnel field-effect transistor (TFET) with a dual metal gate (DMG) as a label-free biosensor has been proposed and analyzed using 3-D technology computer aided design (TCAD) simulations. The article compares the traditional inverted T-type TFET and the inverted T-type TFET with the DMG structure when used as a sensor. We focused on analyzing the electrical characteristics and sensitivity of the DMG structure and the single metal gate (SMG) structure as biosensors. The results show that the inverted T-shaped TFET biosensor with the DMG structure has better sensitivity and electrical characteristics. Compared with the SMG (work function = 4.3 eV), the DMG has a better ON-state current; compared with the SMG (work function = 3.8 eV), the DMG has a better subthreshold swing and sensitivity. In addition, the article also analyzed the influence of factors such as filling degree and temperature on the biosensor. The results show that the higher the filling level, the greater the ON-state current of the sensor. The higher the temperature, the greater the OFF-state current and the lower the sensitivity of the current switching ratio. Finally, a status map is presented, which maps the sensitivities of some important jobs in biosensor applications and the sensitivities of the proposed biosensors. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\text{on}} / I_{\text{off}}$ </tex-math></inline-formula> sensitivity of the inverted T-shaped TFET biosensor is superior to those jobs.

Electrical and Thermal Characteristics of AlGaN/GaN HEMT Devices with Dual Metal Gate Structure: A Theoretical Investigation

The electrical and thermal characteristics of AlGaN/GaN high-electron mobility transistor (HEMT) devices with a dual-metal gate (DMG) structure are investigated by electrothermal simulation and compared with those of conventional single-metal gate (SMG) structure devices. The simulations reveal that the DMG structure devices have a 10-percent higher transconductance than the SMG structure devices when the self-heating effect is considered. In the meantime, employing the DMG structure, a decrease of more than 11% in the maximum temperature rise of the devices can be achieved at the power density of 6 W/mm. Furthermore, the peak in heat generation distribution at the gate edge of the devices is reduced using this structure. These results could be attributed to the change in the electric field distribution at the gate region and the suppression of the self-heating effect. Therefore, the electrical and thermal performances of AlGaN/GaN HEMT devices are improved by adopting the DMG structure.

Suppression of Dissolution Rate via Coordination Complex in Tungsten Chemical Mechanical Planarization

Topography of tungsten should be assured at a minimum through chemical mechanical planarization (CMP) in the metal gate structures (e.g., buried gates, replacement metal gates) and via contact in the middle of line (MOL) process for sub−7 nm semiconductor applications. However, excessive tungsten dissolution during the CMP process that results from high oxidizer concentrations and acidic atmospheres results in poor tungsten topography. In this study, we report a novel strategy to improve the tungsten topography by suppressing tungsten dissolution via coordination complex formations between picolinic acid and tungsten oxide. With 1.5 wt% picolinic acid for the inhibitor, the dissolution rate of tungsten was dramatically attenuated, and improved topography with a Ra value of 7.8 nm were demonstrated while validating CMP removal rate.

Design and Analysis of Junctionless Based Symmetric Nanogap-Embedded TFET Biosensor

In the present paper, symmetrical configuration of dual material double gate dielectric modulated junctionless TFET (DM DG JLTFET) for biosensor applications is explored. The JLTFET consists of Si material with an intensely doped n-type substrate. In this work, the JLTFET utilizes the dielectric modulation method which aids the bio-transistor to recognize neutral and charged analytes (biomolecules). A double metal gate structure is designed by employing two dissimilar metal gate electrodes to reduce short channel impact on device characteristics. The proposed device includes a nanogap region (cavity) which is framed for biomolecules to immobilize. Surface potential and their sensitivity are examined for neutral and charged-neutral analytes. The effects of structure parameters such as nanogap region length and fill-in factor have been analyzed through simulation. The paper examines the behavior of DM DG JLTFET for biological molecules sensing via change in relative permittivity and charge density. The proposed device shows noticeable sensitivity results for charged biomolecules (especially for positively charged analytes). The present work has analyzed the different parameters affecting the sensitivity of the biosensor which includes structural geometric variations like change in cavity length, cavity thickness and fill-in factor. The sensitivity of the neutral biomolecules having higher dielectric constant is observed higher; the surface potential sensitivity of the Gelatin (k = 12) is estimated as 3.75 × 10 3 which is 45%, 55%, and 135% higher than the sensitivity of Keratin (k = 7), Bacteriophage T7 (k = 6), and Glucose Oxidase (k = 3), respectively at the cavity length of 7 nm.

Trap-Induced Data-Retention-Time Degradation of DRAM and Improvement Using Dual Work-Function Metal Gate

Data retention time distribution of the dynamic random-access memory cell transistor of the 20-nm technology generation has been investigated using the physics-based statistical simulation. Traps cause high leakage current of the leaky cells; however, we found that the reduction of trap is not effective in improving the refresh cycle. Therefore, an effective method is needed to overcome the retention time degradation due to the traps. This study shows that the data retention time of the tail cells can be increased more than 50% by adopting the dual work function metal gate structure.

Improvement in DC and pulse characteristics of AlGaN/GaN HEMT by employing dual metal gate structure

This paper presents the fabrication and electrical characterization of dual metal gated high electron mobility transistors (DMG-HEMTs) on AlGaN/GaN/SiC hetero-structure using oblique and normal angle deposition of Nickel and Titanium respectively as gate metals. A noteworthy advance in the device characteristics has been achieved including DC and pulse drain current, transconductance, ON-resistance. The upsurge in DC drain current and transconductance is ∼8% and 11% respectively. Pulse I–V measurements have been executed to evaluate the dynamic performance of DMG-HEMTs. Pulse I–V unveils significant improvement in drain lag, gate lag and current collapse in these devices which is due to the redistribution of electric field under the gate.

Design, Simulation and Performance Analysis of JLTFET Biosensor for High Sensitivity

In this paper, the symmetrical design of a double gate dielectric modulated junctionless tunnel field-effect transistor (DG-DM-JLTFET)-based structure is proposed and investigated and for the first time to inspect label-free recognition of biological molecules like uricase, protein, biotin, aminopropyl-triethoxysilane, etc. The point when biological molecules get immobilized in nanocavity area, the variation in the drain current, subthreshold slope, and ION/IOFF ratio has been used as the detecting parameters to recognize the sensitivity of the DG-DM-JLTFET for biomolecule recognition by using TCAD simulation. A cavity is designed by etching a layer from the substrate, at the side of the gate electrode. A dual metal gate structure is framed by utilizing two unique metal entryway anodes to decrease short channel effects of DG-DM-JLTFET. An examination is exhibited to show the effect of fill-in factor of biological molecules on drain current of DG-DM-JLTFET device. The existence of biological molecules in a small region inside the nanocavity area above the tunneling junction results in the variation of the electrical properties of the device. This brings about high sensitivity in terms of drain current, subthreshold slope, and ION/IOFF ratio. The proposed device structure gives perceptible outcomes for both (neutral and charged) types of biological molecules.

Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor.

P-type two-dimensional steep-slope negative capacitance field-effect transistors are demonstrated for the first time with WSe2 as channel material and ferroelectric hafnium zirconium oxide in gate dielectric stack. F4-TCNQ is used as p-type dopant to suppress electron leakage current and to reduce Schottky barrier width for holes. WSe2 negative capacitance field-effect transistors with and without internal metal gate structures and the internal field-effect transistors are compared and studied. Significant SS reduction is observed in WSe2 negative capacitance field-effect transistors by inserting the ferroelectric hafnium zirconium oxide layer, suggesting the existence of internal amplification (∼10) due to the negative capacitance effect. Subthreshold slope less than 60 mV/dec (as low as 14.4 mV/dec) at room temperature is obtained for both forward and reverse gate voltage sweeps. Negative differential resistance is observed at room temperature on WSe2 negative capacitance field-effect-transistors as the result of negative capacitance induced negative drain-induced-barrier-lowering effect.

An Oxide Chemical Mechanical Planarization Model for HKMG Structures

In order to predict the surface topography, a chip-scale oxide chemical mechanical planarization (CMP) model is proposed in poly opening polishing processing of high-k metal gate (HKMG) structures. A geometrical chemical vapor deposition model is first constructed to describe the influence of design pattern effects on the initial surface profiles of dielectric oxides. Based on contact mechanics, the global pressure distribution is then computed to incorporate the long-range features of design structures and polishing pad deformation. The global pressure is further combined with local pattern effects to construct a feature-scale material removal rate model, which can be utilized for surface topography simulation of design chips. The predicted results of the proposed CMP model are consistent with the experimental data collected from the test patterns of HKMG CMP process. Consequently, the oxide CMP model has good potentials of predicting the surface planarity of polishing wafers and optimizing some design rules for HKMG design layouts.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

High-Performance Plasmonic THz Detector Based on Asymmetric FET With Vertically Integrated Antenna in CMOS Technology

We report a high-performance plasmonic terahertz (THz) detector based on an antenna-coupled asymmetric FET by using the 65-nm CMOS technology. By designing an asymmetric FET on a self-aligned poly-Si gate structure, more enhanced channel charge asymmetry between the source and the drain has been obtained in comparison with the nonself-aligned metal gate structure of our previous paper. In addition, using a vertically integrated patch antenna, which is designed for a 0.2-THz resonance frequency, we demonstrated the highly enhanced detection performance with a responsivity of 1.5 kV/W and a noise-equivalent power of 15 pW/Hz0.5 at 0.2 THz.

Energy-dispersive x-ray spectrum simulation and emprical observation of 22nm node high-k metal gate structure

Energy-dispersive x-ray spectrum simulation and emprical observation of 22nm node high-k metal gate structure

Analog and RF Performance Analysis of a Junctionless Electrically Induced Source/Drain Extension Cylindrical Surround Gate (JLEJ-CSG) MOSFET

Junctionless (JL) transistors have recently been reported as strong candidate for the future technology nodes because of ease of manufacturing and improved performance over conventional MOSFETs. In this paper, the analog and RF performances of a JL transistor have been evaluated with metal gate structure having higher work function in the middle with two side gates of lower work function (electrically induced source/drain junctions, EJ). This triple metal gate JLEJ cylindrical surrounding gate (CSG) MOSFET provides better response in terms of intrinsic gain, transconductance generation factor, early voltage, unity gain transition frequency, maximum frequency of oscillation, etc. over single metal junctionless cylindrical surrounding gate (JLSM) transistors. However, the analog and RF performance metrics have been observed to be degraded because of quantum mechanical effects. The ION/IOFF ratio is improved by more than 105 times.

Novel RF PVD Ti Technology for HAR Structure Applications

Titanium (Ti) liners have been widely used in ULSI technology to improve contact/via resistance. As devices scale down to 32nm and below, Ti extends its application as a wetting layer for planar metal gate and 3D tri-gate structures. To meet the accompanying challenges, a novel RF/DC PVD chamber was developed, operating with capacitively coupled plasma (CCP) and a DC source to create high metal-ion flux with low energy. The new technology reduces overhang and increases bottom coverage. This paper presents the chamber’s tuning knobs that fulfill different process requirements for contact and metal-gate, thereby widening the process window for effective gap fill.

The Effect of Multiple Interfaces on the Electrical Properties of MgO/Al2O3 Multilayer Gate Stacks on Si Grown by MBE

ABSTRACTHigh-κ and metal gate structures have been used to improve the performance of CMOS devices. By changing the materials and structures of the gate dielectric stacks, the flatband voltage (VFB) and the leakage can be changed. We used bilayers and multilayer structures composed of MgO and Al2O3 to verify their influence on the overall electrical properties. Films with an MgO bottom layer generally are found with less flatband voltage shift and lower leakage than with an Al2O3 bottom layer. Also, the frequency dispersion and the interface state density (Dit) are higher for those with MgO bottom layers. MgO films thicker than 0.5 nm effectively shields the positive charges present in the Al2O3.

Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metal-gate stress (MGS) in 20 nm high-k/metal-gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0 to −6 GPa) was implemented in the device simulation along with other traditional process-induced-strain (PIS) technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down. In addition, the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated. Also with a new method of fully stressed replacement metal gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in the metal gate, the process conditions for physical vapor deposition (PVD) TiNx were optimized. The maximum compressive stress of −6.5 GPa TiNx was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.

Defect reduction of replacement metal gate aluminum chemical mechanical planarization at 28 nm technology node

The replacement metal gate (RMG) defectivity control is very challenging for high-k metal gate (HKMG) RMG chemical mechanical polishing (CMP) processes. In this study, three major defect types, including fall on particle, micro-scratch and corrosion, post Al metal CMP process have been investigated to provide the total solutions for preventing the formation of these defects. The fall on particles were fully removed as a repulsive force created between the surfaces of the Al metal gate and polishing abrasives by introducing appropriate acid based slurries and chemical solutions. Furthermore, the micro-scratches could be significantly eliminated as implementing a reliable soft pad at the final polishing step. Severe integranular corrosion and pitting issues on the surface of the RMG structures were also found to be effectively prevented by creating a capable passivation layer with minimized micro-galvanic corrosion level on the top surface of the Ti-doped Al metal gate structures.

Analysis of micro-Raman spectra combined with electromagnetic simulation and stress simulation for local stress distribution in Si devices

We have developed a Raman simulation method using a finite-difference time-domain electromagnetic simulation and a finite element method stress simulation for precise local stress analysis of Si devices. This method accounts for the modification of light distribution by the sample structure, which significantly affects the Raman spectra near a metal gate structure with high refractive index and extinction coefficient. The precise stress estimation by this method is verified by analyzing polarized UV Raman measurements of a metal-oxide semiconductor field-effect transistor structure with a metal gate.