Metal Gate Structure Research Articles

P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

High density plasma etching of titanium nitride metal gate electrodes for fully depleted silicon-on-insulator subthreshold transistor integration

Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions used in this work, the TiN etch rate appears to be ion flux limited and exhibits a low ion enhanced etching activation energy of 0.033eV. Notching of the polysilicon layer above the TiN may occur during the polysilicon overetch step as well as the TiN overetch step. Notching is not significantly affected by charging of the underlying gate dielectric under the conditions used. By optimizing the plasma etch process conditions, TiN:SiO2 selectivity of nearly 1000:1 is achieved, and a two-step TiN main etch and TiN overetch process yields well-defined metal gate structures without severe gate profile artifacts.

Influence of Dry Ashing and Wet Treatments on NVM Metal Gate Structures

Influence of Dry Ashing and Wet Treatments on NVM Metal Gate Structures

Numerical Modeling on Asymmetrical Double-Gate MOSFETs and TiN-Gate FinFETs

Numerical Modeling on Asymmetrical Double-Gate MOSFETs and TiN-Gate FinFETs Han-Geon Kim, Sang-Young Cho, Young-Kyu Kim and Taeyoung Won Department of Electrical Engineering, Inha University, Incheon 402-751 (Received 12 December 2007) We report our numerical study of the device performance of an asymmetric poly-silicon gate n eld e ect transistor (FinFET) and of a FinFET with a TiN metal gate structure. Our numerical simulation revealed that, compared to the conventional FinFET structure, the asymmetric poly-silicon FinFET structures and the TiN-gate FinFET structures exhibited a superior threshold voltage (VT ) tolerance to variations in the n thickness. For instance, the VT tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN-gate FinFET exhibited a 0.015 V tolerance for a 5 nm variation in the n thickness (from 30 to 35 nm) while the conventional FinFET demonstrated a 0.12 V uctuation for the same variation in the n thickness. Our numerical simulation revealed that the VT could be controlled within {0.1 + 0.5 V by varying the doping concentration of the asymmetric poly-silicon gate region from 1.

Performance Comparison between Asymmetric Polycrystalline Silicon Gate and TiN Gate Fin-Shaped Field Effect Transistors

We report our numerical study on the device performance of an asymmetric polycrystalline silicon (poly-Si) gate fin-shaped field effect transistor (FinFET) and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-Si FinFET structures and TiN gate FinFET structures exhibits a superior VT tolerance to the conventional FinFET structure with respect to the variation of fin thickness. For instance, the VT tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation revealed that threshold voltage (VT) can be controlled within - 0.1 to + 0.5 V by the varying of doping concentration of the asymmetric poly-Si gate region from 1.0×1018 to 1.0×1020 cm-3.

3.5-Inch QCIF AMOLED Panels with Ultra-low-Temperature Polycrystalline Silicon Thin Film Transistor on Plastic Substrate

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

Numerical simulation on novel FinFETs: asymmetric poly-silicon gate FinFETs and TiN gate FinFETs

We report our numerical study on the device performance of an asymmetric poly-silicon gate FinFET and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-silicon FinFET structure and TiN gate FinFET structures exhibit superior V T tolerance over the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation further revealed that the threshold voltage (V T) can be controlled within the range of −0.1∼+0.5 V through varying the doping concentration of the asymmetric poly-silicon gate region from 1.0×1018 to 1.0×1020 cm−3.

2-D modeling of potential distribution and threshold voltage of short channel fully depleted dual material gate SOI MESFET

A two-dimensional analytical model for the potential distribution along the bottom channel of the fully depleted region of dual material gate (DMG) SOI MESFET is presented. The potential distribution is modeled by solving the Poisson equation with proper boundary conditions. The model for the potential distribution is extended to derive an analytical expression for the threshold voltage. The accuracy of the model is verified by comparing the analytical results with the results of GENESISe device simulator for different device parameters. The comparison demonstrates an excellent agreement between the analytical and simulation results. The results reveal that the DMG structure introduces a step function in the bottom potential profile in the depleted region. This function reduces the drain induced barrier lowering (DIBL) effect when compared to the conventional single metal gate (SMG) structure. Finally, the effects of different DMG structure parameters on the amount of DIBL reduction are also investigated.

The Influence of the Stacked and Double Material Gate Structures on the Short Channel Effects in SOI MOSFETS

An asymmetric Dual Metal Stack Gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for conventional SOI MOSFETs. The effects of the Stacked Gate (SG) and Dual Metal Gate (DMG) structures on short channel effects are compared. It has been observed that SG reduces DIBL significantly, while DMG prevents the normal roll-off of the threshold voltage reduction.

Wavelength dispersive grazing incidence X-ray fluorescence of multilayer thin films

We developed the grazing incidence X-ray fluorescence (GIXRF) technique based on the wavelength dispersive (WD) fluorescence equipment with a high brilliance synchrotron radiation at SPring-8. With a good energy resolution and a high count rate of the WD detector, a high quality data of an incident angle dependence of fluorescence yields for the composition elements were obtained. Data analysis based on the multilayer model has been developed. On the applications of this technique, two examples are discussed. The interfacial completeness has been evaluated for the 10-layer structure of the giant magnetoresistance (GMR) multilayer. On the other hand, the diffusion of atoms at interface has been evaluated for the Ta 2O 5 metal gate structures.

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance R/sub G/, the metal T-gate FD-SOI MOSFET achieves a higher f/sub max/ of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f/sub T/ of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C/sub gs/ and C/sub gd/ respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

Nanofabrication processes for single-ion implantation of silicon quantum computerdevices

We describe progress in nanofabrication processes for the production ofsilicon-based quantum computer devices. The processes are based on single-ionimplantation to place phosphorus-31 atoms in accurate locations, preciselyself-aligned to metal control gates. These fabrication schemes involvemulti-layer resist and metal structures, electron beam lithography andmulti-angled aluminium shadow evaporation. The key feature of all fabricationschemes is an integrated combination of patterns in different resist andmetal layers that together define self-aligning metal gate structures aswell as channels down to the substrate through which to implant thephosphorus. Central to this process is a new technique that allows forcontrol and detection of the implantation process at a single-ion level.

Increased Thermal Stability of W/Ta2O5 Gate Structure Using Effective Diffusion Barrier of Denuded Tungsten Nitride

We investigated the effect of TiN and WNx diffusion barrier on the thermal stability and electrical properties of W/Ta2O5 gate structure. For TiN/Ta2O5 system annealed at 950°C, both tantalum and oxygen in Ta2O5 films significantly migrated to TiN layer, resulting in the partial oxidation of TiN and the formation of voids in the Ta2O5 layers and increasing the roughness at the TiN/Ta2O5 interface. However, for the WNx/Ta2O5 system annealed even at 950°C, no outdiffusion of tantalum and oxygen from Ta2O5 into annealed-WNx layer was observed. A nitrogen-rich barrier with Ta–O–N bonding formed on Ta2O5 surface during denudation of WNx caused the high thermal stability of WNx/Ta2O5. The electrical characteristics of W/WNx/Ta2O5 system was found to be more superior than that of W/TiN/Ta2O5 in the respect of leakage current and breakdown voltage, thus it can be one of promising metal gate structures with high-dielectric in sub-100 nm metal-oxide semiconductor (MOS) devices.

Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology using low-resistivity (/spl sim/15 /spl mu//spl Omega/cm), bcc (body-centered-cubic)-phase tantalum metal layer has been developed, featuring low-temperature processing below 550/spl deg/C except for gate oxide formation. It was found for the first time that TaNx works not only as a buffer layer which prevents tantalum metal film and gate oxide film from reacting with each other, but also as a seed layer which helps self-growth of bcc-phase tantalum films by hetero-epitaxy. Furthermore, we have demonstrated that the work function of TaNx gate is close to midgap of silicon, hence similar to titanium nitride (TiNx) gate. We have also demonstrated that MOS capacitors on bulk and fully-depleted silicon-on-insulator (FD-SOI) CMOS with TaNx/bcc-Ta/TaNx stacked metal gate structure have excellent electrical characteristics and that the ring-oscillator fabricated using the stacked metal gate CMOS can be operated successfully with 3.8 nm-thickness gate oxide.

Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage.

Illumination-induced inhomogeneity in the carrier density profile of split gate devices

We demonstrate that low-temperature illumination of a GaAs/AlGaAs Hall bar, partially covered by a split metal gate structure, results in the formation of a shallow barrier across the entire device, even in the point contact openings not directly covered by the gates. The minimum carrier density inhomogeneity is determined from the position of the anomalous Hall steps, which are observed even at zero gate voltage as a result of barrier formation. Our results suggest a substantial contribution to the carrier density inhomogeneity, implying that low-temperature illumination may considerably increase disorder in split gate nanostructures.

Electrode structure effect on the selectivity of gas sensors

The effect of the catalytic metal gate structure on the selectivity of MOS gas sensors has been described. It has been shown that hydrogen cyclic treatment (HCT) modifies the structure of the palladium film evaporated on the silicon dioxide. Pore formation in the gate gives rise to the ammonia and carbon monoxide sensitivity of the field-effect sensor. Ammonia adsorption and desorption processes on the sensor surface have been investigated. These processes are of a unimolecular nature with an adsorption activation energy of 0.08±0.02 eV/molecule in an inert atmosphere.

Hydrogenation effects on polysilicon thin-film transistor structures

Summary form only given. The authors have investigated the hydrogenation of various polysilicon TFT (thin-film transistors) structures in a parallel-plate reactor and studied the effect of plasma frequency (30 kHz or 13.56 MHz) on the device characteristics. The device structures included non-self-aligned metal gate, self-aligned polysilicon gate, and offset polysilicon gate. Both polysilicon- and metal-gate structures improved after the hydrogenation at 30 kHz. The subthreshold slope of polysilicon gate TFTs was lower by a factor of two than that of metal gate, showing that the polysilicon gate results in a more efficient hydrogenation of the device structure. The hydrogenation at 13.56 MHz either marginally improves the devices or under certain conditions actually degrades them. Electrical stress of n-channel TFTs (L=10 mu m, W=50 mu m) from the same substrate that were hydrogenated at different plasma frequencies was measured at room temperature under bias stress conditions of V/sub gs/=20 V and V/sub ds/=20 V. The threshold voltage (V/sub T/) was 0.46 V after the 30-kHz hydrogenation and became 0.5 V after stressing for 3*10/sup 4/ s. This decrease in the threshold voltage is indicative of the movement of positive charges in the gate dielectric. >