P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

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With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.