Metal Field Plate Research Articles

Structure Sensitive Hydrogenation Effects in Polysilicon High Voltage thin Film Transistors

AbstractHydrogen passivation of grain boundary and in-grain defects is a key process step in the fabrication of high quality poly-Si TFTs. The sensitivity of the hydrogenation process to device geometry is therefore an important consideration. The effects of rf-plasma hydrogenation on the operating performance of a range of self-aligned and offset drain (Loff = 5 to 40 μm) poly-Si TFT configurations is reported. The hydrogenation of offset drain structures results in a predictable increase in the pre-threshold slope and a reduction in the device threshold voltage. However, extended hydrogenation (up to 12 h) can result in a significant reduction in the device drive current (by up to 2 orders). A similar effect is observed in metal field plate HVTFTs in which some portion of the offset region is un-modulated by the additional electrode. The on state conduction in the offset region is examined as a function of hydrogenation time, temperature and planar electric field. The increase in the on resistance is attributed to a reduction in the poly-Si defect density, which moderates carrier transport through the offset region.

Stepped Gate Polysilicon Thin Film Transistor for Large Area Power Applications

ABSTRACTFor the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

Stepped Gate Polysilicon Thin-Film Transistor for Large Area Power Applications

AbstractFor the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

A four-terminal compact model for high voltage diffused resistors with field plates

This paper presents a four-terminal, physically based, high-voltage diffused resistor model. The model accounts for depletion, inversion, and accumulation at the surface due to the MOS effect of metal field plates, as well as the depletion pinching effect at the sides and bottom of the diffused resistor.

Polycrystalline silicon thin film transistor incorporating a semi-insulating field plate for high voltage circuitry on glass

The fabrication and enhanced performance of a polycrystalline silicon high voltage thin film transistor structure, which incorporates a semi-insulating field plate, are reported. For comparison, the performance of conventional offset drain and metal field plate structures, fabricated on the same wafer using the same low temperature (⩽610 °C) polycrystalline silicon process, is described. Electrical characterization of the high voltage thin film transistor structures demonstrates that the new three terminal device offers the highest blocking capability (>200 V) without sacrificing on state performance.

The effect of metal field plates on multiguard structures with floating p + guard rings

The performance and stability of silicon diode detectors can be improved by implementing guard ring structures around the active detector area. The purpose of this work is to study design parameters influencing the performance of multiguard structures, especially the effect of metal field plates. An important feature is the potential distribution in the multiguard ring structure which depends on the bulk doping concentration, the oxide charge, the size of the gap between guard rings and the field-plate design. We have made a systematic investigation of the effect of distance between floating p + guard rings with two different metal field plate designs. We have also varied the width of the field plates and studied the effect of gamma irradiation. Numerical simulations have been done to compare with results from the experimental potential distributions between guard rings.

Analysis and optimal design of semi-insulator passivated high-voltage field plate structures and comparison with dielectric passivated structures

The influences of the field oxide thickness and the junction depth on the breakdown voltage of semi-insulator passivated planar junctions with the field plate are investigated using a 2D simulator. This is done by analyzing the two extreme situations: the planar junction with an infinitely long field plate, and the deep-depleted MOS structure having a finite size. This rather unconventional approach has offered a new physical insight into the role of the metal field plate and has revealed that the severe field crowding associated with a shallow planar junction can be greatly suppressed by using a thin field oxide. The breakdown voltage and the optimal field oxide thickness of the semi-insulator passivated field plate structures remain nearly constant over a wide variation in the junction depth, and therefore such structures are attractive for realizing high-voltages in vertical devices fabricated by low-voltage IC technology. The influences of the field plate width and the inter-electrode spacing are studied by the conventional approach, and a simple and widely applicable design guideline is given for both the nonpunchthrough and the punchthrough type structures. The influence of the surface charge in the range 0 to 10/sup 12/ cm/sup -2/ is found to be negligible. The semi-insulator passivated and the dielectric passivated field plate structures are compared under optimal conditions. This suggests that the semi-insulator passivated structures are attractive when thin field oxide and a shallow planar junction are needed and that the dielectric passivated structures are better when compactness is desired.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Guard ring design for high voltage operation of silicon detectors

Abstract The termination of the depletion zone towards the non-depleted part of silicon affects the total device leakage current, the long term stability, the noise level and the radiation hardness of silicon detectors. This paper describes computer simulations and experiments to develop guard ring structures for use in silicon detectors requiring thick depletion layers, high operating voltages and biasing beyond depletion without increase in the leakage current and the noise. Computer simulation of a simplified structure is used to understand the influence from the oxide charges and the substrate doping concentration for a segmented guard structure with several floating diffusion strips. Results from the simulations are compared with measurements on devices. The numerical results are found to be in agreement with experimental data. It is found that segmented guard structures with floating diffusion strips have high breakdown voltages and low leakage currents. The effects of floating metal field plates over the oxide between the floating diffusion strips are studied on two different guard structures by measuring the potential on the diffusion strips and the leakage currents in the guard and active diode. The results show that floating intermediate field plates reduces the influence from oxide charges and stabilises the device against environmental influence.

A simpler 100-V polysilicon TFT with improved turn-on characteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process. >

Polysilicon High-Voltage TFT with Field-Plate-Controlled Offset Region

AbstractAn improved polysilicon high voltage thin film transistor (HVTFT) structure with field-plate-controlled offset region (FP-HVTFT) is proposed for eliminating the current-pinching phenomena often observed in the conventional offset-gate polysilicon HVTFTs. The new metal field plate serves, in lieu of ion implantation, to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends of the offset region, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current-pinching effects are consistently obtained. Moreover, the new FP-HVTFT also eliminates the lightly-doped-drain implant normally required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process flow.

Atlanta Fiber System Experiment: Planar Epitaxial Silicon Avalanche Photodiode

A silicon avalanche photodiode (APD) has been developed for optical fiber communications systems. It has been optimized for optical wavelengths of 800 to 850 nm and exhibits a quantum efficiency greater than 90 percent. The APD operates between typical voltages of 100 and 400 V, exhibiting photocurrent gains of approximately 8 and 100, respectively, at those biases. The device has a short response time of ∼ 1 ns and low excess noise characterized by an excess noise factor approximately 5 times the shot noise limit for operation at a photocurrent gain of 100. The APD has a four-layer n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p-π-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> structure and is fabricated on large-diameter epitaxial wafers using planar technology. Uniform avalanche gain, low dark currents, and good reliability are achieved through the use of (i) a diffused guard ring, (ii) a diffused channel stop, (iii) metal field plates, (iv) the removal of impurities in the surface oxides and the bulk of the APD, (v) passivation with silicon nitride and (vi) a processing sequence that maintains low dislocation density material.

A non-destructive method for the measurement of C-V characteristics of MOS capacitors using a gold ball probe

The standard method for sample preparation of MOS capacitors that employs the evaporation of metal field plates ( e.g. gold or aluminium circular dots) followed by back metallization 1 can be substituted by a non-destructive method in which a spring-loaded gold (Au) ball probe is used as a field plate. It is shown that, by incorporating an additional series capacitor to the standard theory of MOS structure, the experimental results obtained by using the Au ball technique can be explained completely. The validity and reliability of this structure for the extraction of the most important information such as Q f (fixed charge), Q o (mobile charge) and Q ss (surface states) were studied and were found to be in very good agreement with those obtained from the conventional structure. The technique also has the practical advantage that no back metallization of the samples is required.

Enhancement of breakdown voltage using floating metal field plates

Avalanche, multiplication factors are calculated for reverse biased p–n junctions with two different junction terminations. One of these is the negative bevel for which it is shown that, by properly locating a metal field plate of the appropriate size on this bevel, it is possible to increase the breakdown voltage of the junction. The field plate is isolated from the semiconductor by a thin dielectric. Since negative bevelled p-n junctions break down in the bulk, the location and size of the field plate must be such that the peak hulk electric field is spread out and reduced. On the other hand, the field plate must be small enough and/or the isolating dielectric thick enough to keep the surface electric fields induced at the field plate edges below the critical value for surface avalanche breakdown. Application in high voltage diodes, power transistors, or thyristors is possible with the floating meta field plate being used to simply increase breakdown voltage or to increase current carrying area (with no...