Memory Interface Research Articles

An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling

An energy-efficient and high-speed mobile memory interface using a novel multilevel dual-band (MDB) signaling is demonstrated. The proposed MDB memory interface that incorporates pulse amplitude modulation (PAM) and RF-band signaling enables simultaneous bidirectional data links through a shared single-ended off-chip transmission line. The PAM and RF-band carries 9.2 and 4.2 Gb/s/pin, respectively. Each RF-band and PAM transceiver consumes 12.6 and 18.4 mW at 1.2 V supply, respectively. The proposed transceiver operates at 13.4 Gb/s/pin with a power efficiency of 2.3 pJ/b/pin and achieves a bit error rate $ with $2^{ {23}} {-}1$ PRBS over a distance of 5 cm. The prototype chip is fabricated in a 65-nm CMOS process with a total area of 0.13 mm $^{2}$ .

LogCA

With the end of Dennard scaling, architects have increasingly turned to special-purpose hardware accelerators to improve the performance and energy efficiency for some applications. Unfortunately, accelerators don't always live up to their expectations and may under-perform in some situations. Understanding the factors which effect the performance of an accelerator is crucial for both architects and programmers early in the design stage. Detailed models can be highly accurate, but often require low-level details which are not available until late in the design cycle. In contrast, simple analytical models can provide useful insights by abstracting away low-level system details. In this paper, we propose LogCA---a high-level performance model for hardware accelerators. LogCA helps both programmers and architects identify performance bounds and design bottlenecks early in the design cycle, and provide insight into which optimizations may alleviate these bottlenecks. We validate our model across a variety of kernels, ranging from sub-linear to super-linear complexities on both on-chip and off-chip accelerators. We also describe the utility of LogCA using two retrospective case studies. First, we discuss the evolution of interface design in SUN/Oracle's encryption accelerators. Second, we discuss the evolution of memory interface design in three different GPU architectures. In both cases, we show that the adopted design optimizations for these machines are similar to LogCA's suggested optimizations. We argue that architects and programmers can use insights from these retrospective studies for improving future designs.

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

This paper describes a 5.8 Gb/s adaptive integrating duobinary decision-feedback equalizer (DFE) for use in next-generation multi-drop memory interface. The proposed receiver combines traditional interface techniques like the integrated signaling and the duobinary signaling, in which the duobinary signal is generated by current integration in the receiver. It can address issues such as input data dependence during integration, need for precursor equalization, high equalizer gain boosting, and sensitivity to high-frequency noise. The proposed receiver also alleviates DFE critical timing to provide gain in speed, and embed DFE taps in duobinary decoding to provide gain in power and area. The adaptation for adjusting the equalizer common-mode level, duobinary zero level, tap coefficient values, and timing recovery is incorporated. The proposed DFE receiver was fabricated in a 45 nm CMOS process, whose measurement results indicated that it worked at 5.8 Gb/s speed in a four-drop channel configuration with seven slave ICs, and the bathtub curve shows 36% open for $10^{-10}$ bit error rate.

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

The design of smart video surveillance systems is an active research field among the computer vision community because of their ability to perform automatic scene analysis by selecting and tracking the objects of interest. In this paper, we present the design and implementation of an FPGA-based standalone working prototype system for real-time tracking of an object of interest in live video streams for such systems. In addition to real-time tracking of the object of interest, the implemented system is also capable of providing purposive automatic camera movement (pan-tilt) in the direction determined by movement of the tracked object. The complete system, including camera interface, DDR2 external memory interface controller, designed object tracking VLSI architecture, camera movement controller and display interface, has been implemented on the Xilinx ML510 (Virtex-5 FX130T) FPGA Board. Our proposed, designed and implemented system robustly tracks the target object present in the scene in real time for standard PAL (720 × 576) resolution color video and automatically controls camera movement in the direction determined by the movement of the tracked object.

Reconfigurable Real Time Signal Capturing through FPGA

Today all communication systems are prototyped on FPGAs before sending them for ASIC backend and fabrication. On other side the FPGAs with million gate logic densities and embedded block RAMs allowed the high speed signal capturing and storage for real time analysis. Performing various functions on the captured data allows high speed spectrum analysis. These two allow the prototyping of complex communication system on FPGA and real time analysis of implemented blocks. There are several types of interface methods possible to communicate the FPGA with a computer.. In this paper novel techniques are implemented for capturing and analyzing the signals of any design on FPGA with configurable UART interface. VHDL will be used for implementation of necessary modules such as block memory, capture FSM, triggering logic and UART interface. Necessary scripts will be developed to generate the synthesizable VHDL code as per the requirements of user. The captured data will be sent to PC using UART. Xilinx ISE will be used for systhesis and performance analysis.

Neural Networks for Time Perception and Working Memory.

Time is an important concept which determines most human behaviors, however questions remain about how time is perceived and which areas of the brain are responsible for time perception. The aim of this study was to evaluate the relationship between time perception and working memory in healthy adults. Functional magnetic resonance imaging (fMRI) was used during the application of a visual paradigm. In all of the conditions, the participants were presented with a moving black rectangle on a gray screen. The rectangle was obstructed by a black bar for a time period and then reappeared again. During different conditions, participants (n = 15, eight male) responded according to the instructions they were given, including details about time and the working memory or dual task requirements. The results showed activations in right dorsolateral prefrontal and right intraparietal cortical networks, together with the anterior cingulate cortex (ACC), anterior insula and basal ganglia (BG) during time perception. On the other hand, working memory engaged the left prefrontal cortex, ACC, left superior parietal cortex, BG and cerebellum activity. Both time perception and working memory were related to a strong peristriate cortical activity. On the other hand, the interaction of time and memory showed activity in the intraparietal sulcus (IPS) and posterior cingulate cortex (PCC). These results support a distributed neural network based model for time perception and that the intraparietal and posterior cingulate areas might play a role in the interface of memory and timing.

TCASM: An asynchronous shared memory interface for high-performance application composition

This paper addresses the growing need for mechanisms supporting intra-node application composition in high-performance computing (HPC) systems. It provides a novel shared memory interface that allows composite applications, two or more coupled applications, to share internal data structures without blocking. This allows independent progress of the applications such that they can proceed in a parallel, overlapped fashion. Composite applications using in-node shared memory can reduce the amount of data to be communicated between nodes, allowing checkpointing and data reduction or analytics to be performed locally and in parallel. The approach is implemented in Linux, and evaluated using benchmarks that represent typical composite applications on a large HPC testbed. The results show that the proposed approach significantly outperforms the traditional ones (up to a 15-fold speed increase on a 200 node machine).

An Intelligence Super Mart Billling System

Abstract Currently embedded systems be mainly based on microcontroller’s i.e. CPUs in the company of included reminiscence the same as well as tangential interface except ordinary microprocessors by means of external chips for memory and peripheral interface circuits are common, especially in technology may not only be useful for streamlining category and supply chains. Nowadays it is rare to see people getting keen in online shopping through e-commerce websites but still the shopping centers are popular. We come across many types of carts used for shopping in malls and shopping center. The major purpose of this effort is reducing delays in foremost supermarkets or shopping center via income of an electronic smart cart method which will introduce an cognitive approach to billing system during RFID technology. Zigbee is base scheduled an IEEE 802.15 ordinary. Zigbee devices a group of pass on data more than longer space by transient data through transitional devices to make more distances ones, create a interconnect network. Purchasing product during a RFID reader going on shopping cart, suggest while product information resolve be stored into EEPROM close to it and EEPROM data spirit send in the direction of central billing system throughout Zigbee module. The anticipated method will survive helpful for avoiding queues in shopping malls for billing. Hence the shopping becomes easy and enjoyable.

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D\u2013Stacked Architecture

Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a customized many-core hardware acceleration platform for short read mapping problems based on hash-index method. The processing core is highly customized to suite both 2-hit string matching and banded Smith-Waterman sequence alignment operations, while distributed memory interface with 3D–stacked architecture provides high bandwidth and low access latency for highly customized dataset partitioning and memory access scheduling. Conformal with original BFAST program, our design provides an amazingly 45,012 times speedup over software approach for single-end short reads and 21,102 times for paired-end short reads, while also beats similar single FPGA solution for 1466 times in case of single end reads. Optimized seed generation gives much better sensitivity while the performance boost is still impressive.

De-Li-DAQ-2D – a new data acquisition system for position-sensitive neutron detectors with delay-line readout

Software for a data acquisition system of modern one- and two-dimensional position-sensitive detectors with delay-line readout, which includes a software interface to a new electronic module De-Li-DAQ-2D with a USB interface, is presented. The new system after successful tests on the stand and on several spectrometers of the IBR-2 reactor has been integrated into the software complex SONIX+ [1]. The De-Li- DAQ-2D module [2] contains an 8-channel time-code converter (TDC-GPX) with a time resolution of 80 ps, field programmable gate array (FPGA), 1 Gbyte histogram memory and high-speed interface with a fiber-optic communication line. A real count rate is no less than 106 events/s. The De-Li-DAQ-2D module is implemented in the NIM standard. The De-Li-DAQ-2D module can operate in two modes: histogram mode and list mode.

Shared Memory Multicore MicroBlaze System with SMP Linux Support

In this work, we present PolyBlaze, a scalable and configurable multicore platform for FPGA-based embedded systems and systems research. PolyBlaze is an extension of the MicroBlaze soft processor, leveraging the configurability of the MicroBlaze and bringing it into the multicore era with Linux Symmetric Multi-Processor (SMP) support. This work details the hardware modifications required for the MicroBlaze processor and its software stack to enable fully validated SMP operations, including atomic operation support, shared interrupts and timers, and exception handling. New in this work, we present a scalable and flexible memory hierarchy optimized for Field Programmable Gate Arrays (FPGAs), which manages atomic operations and provides support for future flexible memory hierarchies and heterogeneous systems. Also new is an in-depth analysis of key performance characteristics, including memory bandwidth, latency, and resource usage. For all system configurations, bandwidth is found to scale linearly with the addition of processor cores until the memory interface is saturated. Additionally, average memory latency remains constant until the memory interface is saturated; after which, it scales linearly with each additional processor core.

Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow

The Memory Access Dataflow execution model and hardware architecture combine principles of decoupled access and execution, dataflow computation, and event-condition-action rules to redevelop the main primitives of an out-of-order core in a power-efficient way that targets memory accesses that naturally occur in programs or get induced when some work is offloaded to an accelerator. Such a mechanism can allow in-core accelerators to integrate with high- or low-performance cores without compromising performance, run at low power by turning off the core during such phases, and provide high energy savings.

A Novel Decode-Aware Compression Technique for Improved Compression and Decompression

With compressed bit streams, more configuration information can be stored using the same memory. The access delay is also reduced, because less bits need to be transferred through the memory interface. To measure the efficiency of bit stream compression, compression ratio (CR) is widely used as a metric. it is a major challenge to develop an efficient compression technique that can significantly reduce the bit stream size without sacrificing the decompression performance. Our approach combines the advantages of previous compression techniques with good compression ratio and those with fast decompression. This paper makes three important contributions. First, it performs smart placement of compressed bit streams to enable fast decompression of variable-length coding. Next, it selects bitmask-based compression parameters suitable for bit stream compression. Finally, it efficiently combines run length encoding and bitmask-based compression to obtain better compression and faster decompression.

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 $\times$ 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

Rambus: A Puzzle to Solve

Anyone who has spent any time with Mark knows that he loves puzzles. His office at Stanford is full of puzzles: some he built himself, some crafted from beautiful hardwood, and some simple children?s toys. Each of them has their own aesthetic and their unique attraction to Mark. So, in many ways, it's no surprise that what attracted him to cofounding Rambus back in 1990 was a puzzle posed by Rambus cofounder Mike Farmwald: could they, using circuit and architecture techniques, increase the bandwidth of the dynamic random access memory (DRAM) interface tenfold without changing process technology?

Using NI PXI Modules for Digital Signal Processing Microprocessor Testing

The article considers the implementation of the external memory interface based on National Instruments modular PXI equipment for environmental testing of digital signal processing (DSP) microprocessors. The block diagram of the developed device pointing out the advantages and disadvantages of this solution is provided. The block diagram of an improved external memory interface is also shown.

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ${{\pm 25\%}}$ range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is ${85\times 60\; \mu {\text{m}^2}}$ and ${150\times 60\; \mu {\text{m}^2}}$ for the TX and RX, respectively.

State-space formulation of scalar Preisach hysteresis model for rapid computation in time domain

A state-space formulation of classical scalar Preisach model (CSPM) of hysteresis is proposed. The introduced state dynamics and memory interface allow to use the state equation, which is rapid in calculation, instead of the original Preisach equation. The main benefit of the proposed modeling approach is the reduced computational effort which requires only a single integration over the instantaneous line segment in the Preisach plane. Numerical evaluations of the computation time and model accuracy are provided in comparison to the CSPM which is taken as a reference model.

Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System

Massively parallel memory systems are designed to deliver high bandwidth at relatively low clock speed for memory-intensive applications implemented on programmable logic. For example, the Convey HC-1 provides 1,024 DRAM banks to each of four FPGAs through a full crossbar, presenting a peak bandwidth of 76.8GB/s to the user logic. Such highly parallel memory systems suffer from high latency, and their effective bandwidth is highly sensitive to access ordering. To achieve high performance, the user must use a customized memory interface that combines scheduling, latency hiding, and data reuse. In this article, we describe the design of a custom memory interface for 3D stencil kernels on the Convey HC-1 that incorporates these features. Experimental results show that the proposed memory interface achieves a speedup in runtime of 2.2 for 6-point stencil and 9.5 for 27-point stencil when compared to a naive memory interface.

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

In this paper, we describe CACTI-IO, an extension to CACTI that includes power, area, and timing models for the IO and PHY of the OFF-chip memory interface for various server and mobile configurations. CACTI-IO enables design space exploration of the OFF-chip IO along with the dynamic random access memory and cache parameters. We describe the models added and four case studies that use CACTI-IO to study the tradeoffs between memory capacity, bandwidth (BW), and power. The case studies show that CACTI-IO helps to: 1) provide IO power numbers that can be fed into a system simulator for accurate power calculations; 2) optimize OFF-chip configurations including the bus width, number of ranks, memory data width, and OFF-chip bus frequency, especially for novel buffer-based topologies; and 3) enable architects to quickly explore new interconnect technologies, including 3-D interconnect. We find that buffers on board and 3-D technologies offer an attractive design space involving power, BW, and capacity when appropriate interconnect parameters are deployed.