Abstract
Today all communication systems are prototyped on FPGAs before sending them for ASIC backend and fabrication. On other side the FPGAs with million gate logic densities and embedded block RAMs allowed the high speed signal capturing and storage for real time analysis. Performing various functions on the captured data allows high speed spectrum analysis. These two allow the prototyping of complex communication system on FPGA and real time analysis of implemented blocks. There are several types of interface methods possible to communicate the FPGA with a computer.. In this paper novel techniques are implemented for capturing and analyzing the signals of any design on FPGA with configurable UART interface. VHDL will be used for implementation of necessary modules such as block memory, capture FSM, triggering logic and UART interface. Necessary scripts will be developed to generate the synthesizable VHDL code as per the requirements of user. The captured data will be sent to PC using UART. Xilinx ISE will be used for systhesis and performance analysis.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Asian Journal of Engineering and Applied Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
