Design and Performance Analysis of 32 Bit VLSI Hybrid adder

Abstract

The Adder circuit is basically required in many application of DSP digital signal processing architecture, Microprocessor, Microcontroller, Filter designing and data Processing units. A system if contains a hybrid adder than it is sure that the system must have low power consumption, high speed (Less delay) and occupies less area space in memory unit. From many years researchers are trying to make devices small in size with high operating speed and Low power consuming so they are trying various techniques In this paper different 32 bit adders are studied and design implementation is done and Some 32 bit hybrid adder are proposed by using various adder combinations, Performance analysis in terms of area (according to the number of LUTs) and delay (in ns) is performed in Xilinx ISE 14.7 using Verilog code.