Abstract
The Memory Access Dataflow execution model and hardware architecture combine principles of decoupled access and execution, dataflow computation, and event-condition-action rules to redevelop the main primitives of an out-of-order core in a power-efficient way that targets memory accesses that naturally occur in programs or get induced when some work is offloaded to an accelerator. Such a mechanism can allow in-core accelerators to integrate with high- or low-performance cores without compromising performance, run at low power by turning off the core during such phases, and provide high energy savings.
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