Memory Error Correction Research Articles

Mathematical model enhancing flash memory reliability through DFT-driven error correction coding

Flash memory, ubiquitous in diverse electronic devices, confronts persistent challenges stemming from inherent errors that jeopardize data integrity. This research situates itself at the intersection of these challenges and advancements, proposing an inventive error correction coding framework that harnesses the unique capabilities of analysis with a hybrid error control coding (HECC) approach. In the proposed work, a mathematical model aimed at enhancing the flash memory by identifying the error pattern within the pages using the discrete fourier transform (DFT). By incorporating distinctive DFT mathematical properties, the proposed technique intends to improve flash memory error correction beyond traditional methods. The flash storage defect detection and rectification results with hybrid error correction coding achieved bit error rate (BER) of 4.3e-6, latency 14.1, mean 15.1 and standard deviation 1.0. Error correction efficiency 98% and storage overhead 10%. With this approach results are significantly improving the error correction efficiency, reduce storage overhead and enhanced adaptability to diverse error patterns.

Searching with a Corrupted Heuristic

Memory-based heuristics are a popular and effective class of admissible heuristic functions. However, corruptions to memory they use may cause these heuristics to become inadmissible. Corruption can be caused by the physical environment due to radiation and network errors, or it can be introduced voluntarily in order to decrease energy consumption. We introduce memory error correction schemes that do not require additional memory and exploit knowledge about the behavior of consistent heuristics. This is in contrast with error correcting code approaches which can limit the amount of corruption but at the cost of additional energy and memory consumption. Search algorithms using our methods are guaranteed to find a solution if one exists and its suboptimality is bounded. Moreover, our methods are resilient to any number of memory errors that may occur. An experimental evaluation is also provided to demonstrate the applicability of our approach.

An Error Location and Correction Method for Memory Based on Data Similarity Analysis

The nanoscale CMOS technology has encountered severe reliability issues, especially in the on-chip memory. As the technology nodes keep shrinking, single-event upsets (SEUs) may encounter more frequent multiple-bit upsets (MBUs) per particle strike. The commonly used memory error correction methods, such as the single-error correction–double-error detection (SEC–DED) code, are no longer feasible. While the counterparts for multiple error correction codes (MECs) yield too costly overhead on delay and data redundancy, especially for MBUs in a word or a character, even with all bits upset, the error correcting ability of the existing error correcting methods is exceeded. In this paper, we introduce a novel block-based error detection and correction method for memory by analyzing the similarity of data. This method of error location and correction can cope with both single-word error (SWE) and multiple-word error (MWE), no matter how many corrupted bits of each word there are. Experimental results on the test system based on SRAM demonstrate that the proposed method can correct single-word–single-bit (SWSB), single-word–multiple-bit (SWMB), multiple-word–single-bit (MWSB), and multiple-word–multiple-bit (MWMB) errors. The proposed method based on block level greatly improved the correction ability with low redundancy, low decoding delay, and moderate complexity versus other homogeneous byte-level or bit-level protection methods. In particular, the detection and correction efficiency is more evident when the data size increases.

Towards Low-Cost Mechanisms to Enable Restoration of Encrypted Non-Volatile Memories

Since Non-Volatile Memories (NVMs) started entering the mainstream memory/storage market, we must consider how to secure NVM-equipped computing systems. Recent Meltdown and Spectre attacks are a strong evidence that security must be intrinsic to computing systems instead of being added as an afterthought. Processor vendors are taking the first steps and are beginning to build security primitives into commodity processors. One security primitive that is associated with the use of emerging NVMs is memory encryption. Memory encryption, while necessary, is very challenging when used with NVMs because it exacerbates the write endurance problem. Secure architectures use cryptographic metadata that must be persisted and restored to allow secure recovery of data in the event of power-loss. Specifically, encryption counters must be persistent to enable secure and functional recovery of an interrupted system. However, the cost of ensuring and maintaining persistence for these counters can be significant. In this paper, we propose a novel scheme to maintain encryption counters without the need for frequent updates. Our new memory controller design, Osiris , repurposes memory Error-Correction Codes (ECCs) to enable fast restoration and recovery of encryption counters. Since different counter-mode encryption schemes are used in industry and research, we provide a versatile Osiris implementation that improves the performance and write-endurance in different memory encryption schemes. To evaluate our design, we use Gem5 to run eight memory-intensive workloads selected from SPEC2006 and U.S. Department of Energy (DoE) proxy applications, and three computation-intensive graph algorithms from CRONO. Compared to a write-through counter-cache scheme, on average, Osiris can reduce 45.8 percent of the memory writes (increase lifetime by 1.86x), and reduce the performance overhead from 44.7 percent(for write-through) to only 4.49 percent. Furthermore, without the need for backup battery or extra power-supply hold-up time, Osiris performs better than a battery-backed write-back (4.4 versus 5.7 percent overhead) and has less write-traffic (1.8 versus 5.4 percent overhead).

Efficient Implementations of 4-Bit Burst Error Correction for Memories

In recent years, there has been a growing interest in error correction codes (ECCs) that can correct localized errors in memories. This is due to the larger fraction of radiation induced error events that affect several nearby memory cells as technology scales. Initially, codes that can correct single and double adjacent errors were proposed. More recently, 3-bit burst ECCs have also been presented. The next step is to provide efficient 4-bit burst error correction for memories. The issue is that as the error correction capability increases so does the overheads required to implement the codes in terms of parity check bits and encoding and decoding complexity. In this brief, efficient solutions to protect memories against 4-bit bursts are presented. The first one is the use of two interleaved single and double adjacent ECC while in the second, efficient 4-bit burst ECCs are presented. The first solution reduces the decoding complexity and delay at the cost of having more parity check bits while the second tries to reduce the decoding complexity when using the minimum number of parity check bits. Both solutions have been evaluated and compared to an interleaved single error correction code and with existing burst ECCs to better understand the overheads needed to achieve the protection against 4-bit burst errors.

Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC

Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density memories are vulnerable to soft errors, memory error correction code (ECC) plays an important role in memory design. In this paper, methods to exploit spare columns including replaced defective columns are proposed to improve memory ECC. To utilize replaced defective columns, the defect information needs to be stored. Two approaches to store defect information are proposed—one is to use a spare column and the other is to use a content-addressable-memory. Experimental results show that the proposed method can significantly enhance the ECC performance.

Features of an Error Correction Memory to Enhance Technical Texts Authoring in LELIE

In this paper, we investigate the notion of error correction memory applied to technical texts. The main purpose is to introduce flexibility and context sensitivity in the detection and the correction of errors related to Constrained Natural Language (CNL) principles. This is realized by enhancing error detection paired with relatively generic correction patterns and contextual correction recommendations. Patterns are induced from previous corrections made by technical for a given type of text. The impact of such an error correction memory is also investigated from the point of view of the technical writers cognitive activity. The notion of error correction memory is developed within the framework of the LELIE project an experiment is carried out on the case of fuzzy lexical items and negation, which are both major problems in technical writing. Language processing and knowledge representation aspects are developed together with evaluation directions.

English

The proposed security code utilizes decimal method to detect errors, so that more errors were detected and corrected. At the present days to maintain good level of reliability, it is required to protect memory cells using protection codes, for this purpose, various error detection and correction methods are being used. In the paper 64-bit Decimal Matrix Code was proposed to assure the dependability of memory. Here to detect and correct up to 50% errors. The results showed that the proposed scheme has a protection level against large MCUs in memory. To avoid MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would need higher delay overhead. Previously, matrix codes (MCs) based on Hamming codes include been proposed for memory safety. The main problem is that they are double error correction codes and the error correction capabilities are not enhanced in each case. Transient multiple cell upsets (MCUs) are appropriate major problems in the reliability of memories exposed to energy environment. In the new method we are implement 64-bit decimal matrix for error correction in memories. In the new method to increase the error correction rate compared to the 32-bit decimal matrix code. Moreover, the ERT (encoder-reuse technique) is proposed to decrease the area transparency of extra circuits exclusive of disturbing the total encoding and decoding processes. ERT (encoder re use technique) use DMC encoder itself to be part of in the decoder.

Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications

In this Paper, we focus on a class of LDPC codes known as Euclidean Geometric (EG) LDPC codes, which are constructed deterministically using the points and lines of a Euclidean geometry. Minimum distances for EG codes are also reasonably good and can be derived analytically. memory error correction code has been implemented using pipelined cyclic corrector where majority logic gate determined the error .LDPC soft error decoding is also implemented for the same memory error detection and correction comparison of the results are done .as the majority gate can detect only upto 2 error the extending majority gate with ldpc soft decoding can decrease the bit error rate.

다목적 Error Correcting Code의 새로운 설계방법

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

Reducing Power in Error Correcting Code using Genetic Algorithm

Abstract — This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method. Keywords — Error correcting codes, genetic algorithm, non-linear power optimization, Hamming code, Hsiao code.I. I NTRODUCTION S technology continues to scal e with smaller features sizes, lower power supply voltages, and higher operating frequencies, the soft error rate in logic circuits is rapidly increasing. Concurrent error detection using error correcting codes (ECCs) at the outputs of a circuit provides means to detect soft errors quickly before they have a chance to propagate and compromise the data integrity of a system. Error correcting codes are commonly used to protect against soft errors and thereby enhance system reliability and data integrity [1]. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. These codes are able to correct single-bit errors and detect double-bit errors in a codeword. A design criterion that has become very important in recent times is power reduction. With increasing miniaturization of devices, power has become a first-order design consideration motivating researchers to look at techniques of reducing power consumption in all components of system design. For memory ECC, power reduction is also an important consideration, since the ECC checker circuit is activated during reading and writing access to the memory. As power has become an important consideration, researchers have begun looking at methods to reduce power consumption in error detection circuitry [2-4].