An Error Location and Correction Method for Memory Based on Data Similarity Analysis

Abstract

The nanoscale CMOS technology has encountered severe reliability issues, especially in the on-chip memory. As the technology nodes keep shrinking, single-event upsets (SEUs) may encounter more frequent multiple-bit upsets (MBUs) per particle strike. The commonly used memory error correction methods, such as the single-error correction–double-error detection (SEC–DED) code, are no longer feasible. While the counterparts for multiple error correction codes (MECs) yield too costly overhead on delay and data redundancy, especially for MBUs in a word or a character, even with all bits upset, the error correcting ability of the existing error correcting methods is exceeded. In this paper, we introduce a novel block-based error detection and correction method for memory by analyzing the similarity of data. This method of error location and correction can cope with both single-word error (SWE) and multiple-word error (MWE), no matter how many corrupted bits of each word there are. Experimental results on the test system based on SRAM demonstrate that the proposed method can correct single-word–single-bit (SWSB), single-word–multiple-bit (SWMB), multiple-word–single-bit (MWSB), and multiple-word–multiple-bit (MWMB) errors. The proposed method based on block level greatly improved the correction ability with low redundancy, low decoding delay, and moderate complexity versus other homogeneous byte-level or bit-level protection methods. In particular, the detection and correction efficiency is more evident when the data size increases.