Configuration Memory Research Articles

Non-Markovian rate theory on a multidimensional reaction surface: Complex interplay between enhanced configuration space and memory

A theory of barrier crossing rate on a multidimensional reaction energy surface is presented. The theory is a generalization of the earlier theoretical schemes to higher dimensions, with the inclusion of non-Markovian friction along both the reactive and the nonreactive coordinates. The theory additionally includes the bilinear coupling between the reactive and the nonreactive modes at the Hamiltonian level. Under suitable conditions, we recover the rate expressions of Langer and Hynes and establish a connection with the rate treatment of Pollak. Within the phenomenology of generalized Langevin equation description, our formulation provides an improvement over the existing ones because we explicitly include both the non-Markovian effects along the reaction coordinate and the bilinear coupling at the Hamiltonian level. At intermediate-to-large friction, an increase in dimensionality by itself tends to reduce the rate, while the inclusion of the memory effects increases the rate. The theory predicts an increase in rate when off-diagonal friction terms are included. We present a model calculation to study isomerization of a stilbene-like molecule using the prescription of Hochstrasser and co-workers on a two-dimensional reaction energy surface, employing Zwanzig-Bixon hydrodynamic theory of frequency-dependent friction. The calculated rate shows a departure from the predictions of Langer's theory and also from the two-dimensional transition state theory.

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.

SmartApprox: Learning-based configuration of approximate memories for energy-efficient execution

Approximate memories reduce power and increase energy efficiency, at the expense of errors in stored data. These errors may be tolerated, up to a point, by many applications with negligible impact on the quality of results. Uncontrolled errors in memory may, however, lead to crashes or broken outputs. Error rates are determined by fabrication and operation parameters, and error tolerance depends on algorithms, implementation, and inputs. An ideal configuration features parameters for approximate memory that minimize energy while allowing applications to produce acceptable results. This work introduces SmartApprox, a framework that configures approximation levels based on features of applications. In SmartApprox, a training phase executes a set of applications under different approximation settings, building a knowledge base that correlates application features (e.g., types of instructions and cache efficiency) with suitable approximate memory configurations. At runtime, features of new applications are sampled and approximation knobs are adjusted to correspond to the predicted error tolerance, according to existing knowledge and the current error scenario, in consonance with hardware characterization. In this work, we list and discuss sets of features that influence the approximation results and measure their impact on the error tolerance or applications. We evaluate SmartApprox on different voltage-scaled DRAM scenarios using a knowledge base of 26 applications, wherein energy savings of 36% are possible with acceptable output. An evaluation using a combined energy and quality metric shows that SmartApprox scores 97% of an exhaustive search for ideal configurations, with significantly lower effort and without application-specific quality evaluation.

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

Fault emulation in field-programmable gate arrays (FPGAs) is a popular alternative to test the reliability of a design due to its low cost and high availability compared to traditional radiation-based approaches. Fault emulation is an instrumentation method based on inducing artificial bit flips on the design under test (DUT) to modify the content of its memory elements or the structure of the design itself. A major limitation of error emulation in FPGAs lies in the determination of the proper bits to test, which is directly related to the reliability results obtained and the execution times of the fault injection campaign. The Automatic Configuration Memory Error-injection (ACME) tool helps with this process in Xilinx FPGAs by obtaining the essential bits of an FPGA region where the DUT is. In this paper, we present ACME-2, an improved version of the tool where the translation from the FPGA region to design essential bits has been modified with architectural information of the FPGA. In this revision of the tool, redundant input/output routing bits that distort the reliability results are minimized. For the example designs used in the experiments, these modifications have led to an improvement in the precision of the reliability results as well as a reduction of the fault injection campaign runtime over the previous version of the tool.

Reliability evaluation of FPGA based pruned neural networks

Convolutional Neural Networks (CNNs) are widely used for image classification. To fit the implementation of CNNs on resource-limited systems like FPGAs, pruning is a popular technique to reduce the complexity. In this paper, the robustness of the pruned CNNs against errors on weights and configuration memory of the FPGA accelerator is evaluated with VGG16 as a case study, and two popular pruning methods (magnitude-based and filter pruning) are considered. In particular, the accuracy loss of the original VGG16 and the ones with different pruning rates is tested based on fault injection experiments, and the results show that the effect of errors on weights and configuration memories are different for the two pruning methods. For errors on weights, the networks pruned using both methods demonstrate higher reliability with higher pruning rates, but the ones using filter pruning are relatively less reliable. For errors on configuration memory, errors on about 30% of the configuration bits will affect the CNN operation, and only 14% of them will introduce significant accuracy loss. However, the effect of the same critical bits is different for the two pruning methods. The pruned networks using magnitude-based method are less reliable than the original VGG16, but the ones using filter pruning are more reliable than the original VGG16. The different effects are explained based on the structure of the CNN accelerator and the properties of the two pruning methods. The impact of quantization on the CNN reliability is also evaluated for the magnitude-based pruning method.

An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

Reliability in microelectronics is an important factor in high radiation environments, such as in space, particularly in SRAM-based FPGAs where a Single Event Upset (SEU) in the configuration memory can have drastic effects on the connections of implemented designs. As technology advances and components reduce in size with lower operating powers, SEUs can occur more frequently. An SEU in the configuration memory is permanent unless the associated bit is rewritten either by a full reconfiguration or configuration memory scrubbing. In this paper we discuss a phenomenon that we call secondary critical bits (SCBs), in which certain bits or frames have a chance of causing functional failures if an SEU already exists in the system without a functional failure, and a new metric, frame criticality that can be used for a more fine-grained analysis of a designs reliability. We present a novel frame based statistical double bit fault injection method to analyse the frame criticality in a feasible amount of time. Also presented is a passive configuration memory scrubbing scheme that offers greater protection against this phenomenon compared with traditional blind techniques with improvements up to 65%, for higher SEU rates and more sensitive components.

Civilizational mnemonics and the longue durée: The Bulgarian case

Constructivist assumptions have dominated the field of memory studies, producing an avalanche of case studies focusing on the instrumental and expedient factors shaping memory politics. However, this constructivist bias has also yielded new blind spots. For one, it tends to privilege “events” and “contingencies” over the longue durée of a particular memory configuration. Two, it remains caught in a binary juxtaposition with some states adopting globally circulating mnemonic scripts, signaling universal aspirations, while other states pursue nation-centric approaches. To overcome these blind spots (and binaries), we propose two interrelated conceptual moves: first, we are taking the importance of enduring memory figurations into consideration. Second, we expand the nation-state focus by introducing the notion of “civilizational mnemonics,” which does not replace national memories, but frequently underwrites them. Bulgarian memory politics, our test case, is part of a complex nexus of imperial legacies and post-colonial discourses. Bulgaria has been a middle ground, accommodating competing imperial projects—Ottoman, Russian, and Western. These intersections allow us to draw general inferences about mnemonic tropes and their enduring salience.

Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to SEUs. For applications demanding high reliability this problem is often solved by integrating in the system a scrubber, a circuit that periodically scans the FPGA configuration memory and reconfigures it if an error is detected. Since the scrubber is usually implemented in the same FPGA device, it is also vulnerable to SEUs, thus the scrubber reliability is increased by adopting standard fault tolerance techniques. These solutions guarantee the scrubber reliability, but generally require a large area overhead.In this paper, we present a novel low-cost strategy capable to detect faults in the FPGA configuration memory implementing the scrubber. The proposed technique is based on time redundancy, forcing the scrubber output to produce an error indication for each word read from the FPGA memory, in order to detect the faults affecting the portion of FPGA memory implementing the scrubber. The implementation of our proposed strategy presents a negligible impact in terms of area overhead (4.17%) and a limited increase in power consumption (22.9%) over the original (unprotected) scrubber. As for the impact on system performance introduced by our strategy, it is of approximately the 38.2% over the unprotected scrubber, but it can be significantly lowered by reducing the frequency at which the scrubber is applied to test the FPGA.

Exploring FPGA Logic Block Architecture for Reduced Configuration Memory

Exploring FPGA Logic Block Architecture for Reduced Configuration Memory

Fault injection and failure analysis on Xilinx 16 nm FinFET Ultrascale+ MPSoC

Energetic particle strikes the device and induces data corruption in the configuration memory (CRAM), causing errors and even malfunctions in a system on chip (SoC). Software-based fault injection is a convenient way to assess device performance. In this paper, dynamic partial reconfiguration (DPR) is adopted to make fault injection on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. And the reconfiguration module implements the Sobel and Gaussian image filtering, respectively. Fault injections are executed on the static and reconfiguration modules' bitstreams, respectively. Another contribution is that the failure modes and effects analysis (FMEA) method is applied to evaluate the system reliability, according to the obtained injection results. This paper proposes a software-based solution to estimate programmable device vulnerability.

The Impact of Terrestrial Radiation on FPGAs in Data Centers

Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

Revisiting active object stores: Bringing data locality to the limit with NVM

Object stores are widely used software stacks that achieve excellent scale-out with a well-defined interface and robust performance. However, their traditional get/put interface is unable to exploit data locality at its fullest, and limits reaching its peak performance. In particular, there is one way to improve data locality that has not yet achieved mainstream adoption: the active object store. Although there are some projects that have implemented the main idea of the active object store such as Swift’s Storlets or Ceph Object Classes, the scope of these implementations is limited.We believe that there is a huge potential for active object stores in the current status quo. Hyper-converged nodes are bringing more computing capabilities to storage nodes — and vice versa. The proliferation of non-volatile memory (NVM) technology is blurring the line between system memory (fast and scarce) and block devices (slow and abundant). More and more applications need to manage a sheer amount of data (data analytics, Big Data, Machine Learning & AI, etc.), demanding bigger clusters and more complex computations. All these elements are potential game changers that need to be evaluated in the scope of active object stores.More specifically, having NVM devices presents additional opportunities, such as in-place execution. Being able to use the NVM from within the storage system while taking advantage of in-place execution (thanks to the byte-addressable nature of the NVM), in conjunction with the computing capabilities of hyper-converged nodes, can lead to active object stores that greatly outperform their non-active counterparts.In this article we propose an active object store software stack and evaluate it on an NVM-populated node. We will show how this setup is able to reduce execution times from 10% up to more than 90% in a variety of representative application scenarios. Our discussion will focus on the active aspect of the system as well as on the implications of the memory configuration.

Charge Configuration Memory (CCM) Device – A Novel Approach to Memory

Computer technologies have advanced unimaginably over the last 70 years, mainly due to scaling of electrical components down to the nanometre regime and their consequential increase in density, speed and performance. Decrease in dimensions also brings about many unwanted side effects, such as increased leakage, heat dissipation and increased cost of production [1], [2]. However, it seems that one of the biggest factors limiting further progress in high-performance computing is the increasing difference in performance between processors and memory units, a so called processor-memory gap [3]. To increase the efficiency of memory devices, emerging alternative non-volatile memory (NVM) technologies could be introduced, promising high operational speed, low power consumption and high density [4]. This review focuses on a conceptually unique non-volatile Charge Configuration Memory (CCM) device, which is based on resistive switching between different electronic states in a 1T-TaS 2 crystal [5]. CCM demonstrates ultrafast switching speed <16 ps, very low switching energy (2.2 fJ/bit), very good endurance [6] and a straightforward design. It operates at cryogenic temperatures, which makes it ideal for integration into emerging cryo-computing [7] and other high-performance computing systems such as superconducting quantum computers.

Evaluating softcore GPU in SRAM-based FPGA under radiation-induced effects

This work investigates selective mitigation techniques to improve the reliability of a configurable open-source softcore GPU implemented in an SRAM-based FPGA against configuration memory faults. It explores the unhardened and hardened reliability curves of isolated groups of the target GPU's modules to guide the decision of the best candidates for selective hardening. Fault injection campaigns are performed on the target GPU running three case-study applications by accumulating radiation-induced effects in the FPGA's configuration memory. Individual modules' reliability curves are combined with their resource usages to selectively harden a larger area of the target GPU and increase reliability/area effectiveness. Results can help designers in hardening configurable GPUs for a given application more effectively.

Identifying Radiation-Induced Micro-SEFIs in SRAM FPGAs

Field-programmable gate arrays (FPGAs) are susceptible to radiation-induced effects that can affect more than one memory cell. Radiation-induced microsingle event functional interrupts (micro-SEFIs) are one of such events that can upset several bits at a time. These events need to be studied because they can overcome protection from techniques such as triple modular redundancy (TMR) and error correction codes (ECCs). Extracting these events from radiation data helps to understand if specific resources of the FPGA are more vulnerable and the extent of this vulnerability. This article presents a method based on statistics and fault injection to identify micro-SEFIs from beam-test data in the configuration memory and block RAM (BRAM) of SRAM-based FPGAs. The results show the cross section of these events for the configuration RAM (CRAM) and BRAM for three families of Xilinx SRAM FPGAs gathered throughout three neutron tests. This article also contains data from a fault injection campaign to uncover the possible CRAM source bits causing micro-SEFIs in memory look-up tables (LUTs) of Xilinx 7-series and Ultrascale devices.

A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing

Hyperdimensional computing (HDC) is a brain-inspired computing paradigm-based on high-dimensional holistic representations of vectors. It recently gained attention for embedded smart sensing due to its inherent error-resiliency and suitability to highly parallel hardware implementations. In this work, we propose a programmable all-digital CMOS implementation of a fully autonomous HDC accelerator for always-on classification in energy-constrained sensor nodes. By using energy-efficient standard cell memory (SCM), the design is easily cross-technology mappable. It achieves extremely low power, 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> in typical applications, and an energy efficiency improvement over the state-of-the-art (SoA) digital architectures of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> in post-layout simulations for always-on wearable tasks such as Electromyography (EMG) hand gesture recognition. As part of the accelerator’s architecture, we introduce novel hardware-friendly embodiments of common HDC-algorithmic primitives, which results in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3\times $ </tex-math></inline-formula> technology scaled area reduction over the SoA, achieving the same accuracy levels in all examined targets. The proposed architecture also has a fully configurable datapath using microcode optimized for HDC stored on an integrated SCM-based configuration memory, making the design “general-purpose” in terms of HDC algorithm flexibility. This flexibility allows usage of the accelerator across novel HDC tasks, for instance, a newly designed HDC-algorithm for the task of ball bearing fault detection.

Continuous attractors for dynamic memories.

Episodic memory has a dynamic nature: when we recall past episodes, we retrieve not only their content, but also their temporal structure. The phenomenon of replay, in the hippocampus of mammals, offers a remarkable example of this temporal dynamics. However, most quantitative models of memory treat memories as static configurations, neglecting the temporal unfolding of the retrieval process. Here, we introduce a continuous attractor network model with a memory-dependent asymmetric component in the synaptic connectivity, which spontaneously breaks the equilibrium of the memory configurations and produces dynamic retrieval. The detailed analysis of the model with analytical calculations and numerical simulations shows that it can robustly retrieve multiple dynamical memories, and that this feature is largely independent of the details of its implementation. By calculating the storage capacity, we show that the dynamic component does not impair memory capacity, and can even enhance it in certain regimes.

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification

This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.

Emulating Radiation-Induced Multicell Upset Patterns in SRAM FPGAs With Fault Injection

Radiation-induced multiple-cell upsets (MCUs) are events that account for more than 50% of failures on triple modular redundancy (TMR) designs in SRAM field programmable gate array (FPGA). It is important to understand these events and their impact on FPGA designs to develop improved fault mitigation techniques. This article describes an enhanced fault injection (FI) method for SRAM-based FPGAs that injects MCUs within the configuration memory of an FPGA based on MCU information extracted from previous radiation tests. The improved FI technique uncovers 3× more failures than is observable in conventional single-bit FI approaches. The results from several MCU FI experiments also show that injecting MCUs can replicate the failures observed in the radiation beam test and identify new failure mechanisms.