Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to SEUs. For applications demanding high reliability this problem is often solved by integrating in the system a scrubber, a circuit that periodically scans the FPGA configuration memory and reconfigures it if an error is detected. Since the scrubber is usually implemented in the same FPGA device, it is also vulnerable to SEUs, thus the scrubber reliability is increased by adopting standard fault tolerance techniques. These solutions guarantee the scrubber reliability, but generally require a large area overhead.In this paper, we present a novel low-cost strategy capable to detect faults in the FPGA configuration memory implementing the scrubber. The proposed technique is based on time redundancy, forcing the scrubber output to produce an error indication for each word read from the FPGA memory, in order to detect the faults affecting the portion of FPGA memory implementing the scrubber. The implementation of our proposed strategy presents a negligible impact in terms of area overhead (4.17%) and a limited increase in power consumption (22.9%) over the original (unprotected) scrubber. As for the impact on system performance introduced by our strategy, it is of approximately the 38.2% over the unprotected scrubber, but it can be significantly lowered by reducing the frequency at which the scrubber is applied to test the FPGA.