An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

Abstract

Reliability in microelectronics is an important factor in high radiation environments, such as in space, particularly in SRAM-based FPGAs where a Single Event Upset (SEU) in the configuration memory can have drastic effects on the connections of implemented designs. As technology advances and components reduce in size with lower operating powers, SEUs can occur more frequently. An SEU in the configuration memory is permanent unless the associated bit is rewritten either by a full reconfiguration or configuration memory scrubbing. In this paper we discuss a phenomenon that we call secondary critical bits (SCBs), in which certain bits or frames have a chance of causing functional failures if an SEU already exists in the system without a functional failure, and a new metric, frame criticality that can be used for a more fine-grained analysis of a designs reliability. We present a novel frame based statistical double bit fault injection method to analyse the frame criticality in a feasible amount of time. Also presented is a passive configuration memory scrubbing scheme that offers greater protection against this phenomenon compared with traditional blind techniques with improvements up to 65%, for higher SEU rates and more sensitive components.