MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity

Abstract

SRAM-based FPGAs are widely used for developing many critical systems due to their huge capacity, flexibility, and high performance. However, their applicability in the presence of the Single Event Upsets (SEUs) should be ensured using mitigation techniques for specific critical systems e.g. space applications or automotive industry. Among all existing mitigation techniques, the scrubbing scheme is considered the most reliable technique that particularly avoids SEU accumulation in Configuration Memory (CM) that is the most SEU vulnerable component in an SRAM-based FPGAs. In spite of that, the error repair time realized by Mean Time to Repair (MTTR) attained by scrubbing is a pressing concern for real-time systems. To reduce MTTR, the impact of SEU in CM bits on correct circuit operation is considered in state-of-the-art scrubbing methods. In this paper, we examine the MTTR reduction taking into account multiple proposed precision levels to identify CM sensitive bits; i.e. bits have an adverse impact on correct circuit operation when infected by SEU. Two scrubbing methods are proposed based on these precision levels. Experimental results show an average of 20% \\45% \\46.5% MTTR reduction if the proposed precision-aware scrubbing methods taking into account sensitive bits recognized with low \\medium \\high precision compared to with very low precision. Experiments also show that higher MTTR reduction was achievable for non uniform structure like FFT (i.e about 68%). Thus the cost of distinguishing sensitive bits with higher precision is worth only when the circuit has a non-uniform structure in CM.