Configuration Memory Research Articles

SEAMS

Memory approximation techniques are commonly limited in scope, targeting individual levels of the memory hierarchy. Existing approximation techniques for a full memory hierarchy determine optimal configurations at design-time provided a goal and application. Such policies are rigid: they cannot adapt to unknown workloads and must be redesigned for different memory configurations and technologies. We propose SEAMS: the first self-optimizing runtime manager for coordinating configurable approximation knobs across all levels of the memory hierarchy. SEAMS continuously updates and optimizes its approximation management policy throughout runtime for diverse workloads. SEAMS optimizes the approximate memory configuration to minimize energy consumption without compromising the quality threshold specified by application developers. SEAMS can (1) learn a policy at runtime to manage variable application quality of service ( QoS ) constraints, (2) automatically optimize for a target metric within those constraints, and (3) coordinate runtime decisions for interdependent knobs and subsystems. We demonstrate SEAMS’ ability to efficiently provide functions (1)–(3) on a RISC-V Linux platform with approximate memory segments in the on-chip cache and main memory. We demonstrate SEAMS’ ability to save up to 37% energy in the memory subsystem without any design-time overhead. We show SEAMS’ ability to reduce QoS violations by 75% with < 5% additional energy.

UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory

During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.

Ultrafast non-thermal and thermal switching in charge configuration memory devices based on 1T-TaS2

Charge configuration memory (CCM) device operation is based on the controllable reconfiguration of electronic domains in a charge-density-wave material. Since the dominant effect involves the manipulation of electrons rather than atoms, the devices can display sub-picosecond switching speed and ultralow, few femtojoule switching energy. The mechanisms involved in switching between domain states of different electrical resistances are highly non-trivial and involve trapping non-equilibrium charges within topologically protected domain states. Here, we discuss the underlying physics that are deemed essential for the operation of CCM devices, focusing on the unusual asymmetry between non-thermal “write” processes and thermal “erase” processes from the point of view of the mechanism in relation to the thermal dynamics.

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration

CMOS compatible spin-transfer-torque magnetic random access memory (STT-MRAM) has demonstrated promising developments as the next-generation embedded non-volatile memory (eNVM). In this survey, we provide the state-of-the-art multi-modes reconfigurable techniques for energy-efficient STT-MRAM implementation. We resort to the bottom-up design approach with a twofold aim: 1) summarizing related work from bit-cell to circuit and system levels with conventional and emerging memories. 2) analyzing the present research status of multi-modes reconfigurable techniques in MRAM, which consist of tunable bit-cell configuration, in-memory computing and hybrid memory system. Experimental comparisons show that both reconfiguration and in-MRAM computing obtain extra design freedom. Nonvolatile data accessing cost can be well-alleviated, and thereby improving energy efficiency of MRAM.

Configural learning memory can be transformed from intermediate-term to long-term in pond snail Lymnaea stagnalis

A lab bred W-strain of Lymnaea stagnalis exhibits configural learning (CL). CL is a form of higher order associative learning wherein when snails experience two contrasting stimuli together such as predatory odour (CE: crayfish effluent) and food odour (C: carrot odour) they learn and associate risk with food. The memory for CL has been shown to last 3 h. Here, we show that when only a single CL-training session is given only a 3 h memory is formed. Memory is not present 24 h after the training session. However, memory can be enhanced and snails show long term memory (24 h memory) when trained for a second time within a 7-day time period after the first CL-training. We further hypothesised that Green tea exposure will enhance memory persistence as catechins in green tea are shown to be cognitive enhancers. We thus subjected snails to CL training followed by green tea exposure which resulted in enhanced memory persistence and it occurred during memory consolidation phase. Thus, we show for the first time that CL intermediate-term memory can be transformed to long-term memory by green tea and multiple trainings in a lab bred strain of Lymnaea.

Emerging 2D Memory Devices for In-Memory Computing.

It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.

Amnesia, aphasia and amnesty: the articulations of Italian colonial memory in postwar films (1946–1960)

This article aims to expose the political and cultural processes that contributed to the eradication of problematic memories of the Italian colonial period during the national reconstruction following the Second World War. It offers a systematic examination of newsreels and documentaries about the Italian former colonies that were produced between 1946 and 1960, a film corpus that has largely been neglected by previous scholarship. The article first dissects the ambiguous political scenario that characterised the production of this footage through the study of original archival findings. The footage configured a particular form of self-exculpatory memory, which obstructed a thorough critique of the colonial period while articulating a new discourse about the future presence of Italy in the former colonies. This seems to be a case of aphasia rather than amnesia, insofar as the films addressed not an absence, but an inability to comprehend and articulate a critical discourse about the past. This aphasic configuration of colonial memories will be tackled through a close reading of the voice-over and commentary. In so doing, this work suggests that the footage actively contributed to spread un-problematised narratives and memories about the colonial period, whose results still infiltrate Italian contemporary society, politics and culture.

Enabling Homomorphically Encrypted Inference for Large DNN Models

The proliferation of machine learning services in the last few years has raised data privacy concerns. Homomorphic encryption (HE) enables inference using encrypted data but it incurs 100x-10,000x memory and runtime overheads. Secure deep neural network (DNN) inference using HE is currently limited by computing and memory resources, with frameworks requiring hundreds of gigabytes of DRAM to evaluate small models. To overcome these limitations, in this paper we explore the feasibility of leveraging hybrid memory systems comprised of DRAM and persistent memory. In particular, we explore the recently-released Intel Optane PMem technology and the Intel HE-Transformer nGraph to run large neural networks such as MobileNetV2 (in its largest variant) and ResNet-50 for the first time in the literature. We present an in-depth analysis of the efficiency of the executions with different hardware and software configurations. Our results conclude that DNN inference using HE incurs on friendly access patterns for this memory configuration, yielding efficient executions.

Configurable memory designs in quantum-dot cellular automata

Configurable memory designs in quantum-dot cellular automata

Reliability assessment on 16 nm ultrascale+ MPSoC using fault injection and fault tree analysis

A methodology is proposed to emulate and assess the single event effect in configuration memory on 16 nm Ultrascale+ MPSoC. The solution depends on fault injection and fault tree analysis. Three image processing applications, including histogram computation, image stretch and sobel edge detection, are used as the benchmarks. The results demonstrate 38.1% to 40.5% system errors cannot be recovered, although the SEM sub-system is adopted to recover the corresponding upset in the configuration memory.

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

Partial TMR for Improving the Soft Error Reliability of SRAM-Based FPGA Designs

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit-cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly.

Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems

Shared memory architectures, as opposed to private-only memories, provide a viable alternative to meet the ever-increasing memory requirements of multi-accelerator systems to achieve high performance under stringent area and energy constraints. However, an impulsive memory sharing degrades performance due to network contention and latency to access shared memory. We propose the Accelerator Shared Memory (ASM) framework to provide an optimal private/shared memory configuration and shared data allocation under a system’s resource and network constraints. Evaluations show ASM provides up to 34.35% and 31.34% improvement in performance and energy, respectively, over baseline systems.

Emulating artificial neuron and synaptic properties with SiO2-based memristive devices by tuning threshold and bipolar switching effects

The implementation of neuromorphic computations within a fully memristive neural network is considered the holy grail of the artificial intelligence era. In order to attain this goal, it is quite important to develop robust and configurable electronic devices capable of emulating spiking neuronal and synaptic plasticity activities. Along these lines, we report here the direct impact of oxygen concentration as well as of the homo-bilayer material configuration of SiO2-conductive bridge memories to the manifestation of tunable threshold and bipolar switching effects. Interestingly, while the bilayer structure of Ag/SiO x /SiO y /TiN (x < y) exhibits only bipolar switching effect, the respective single-layer structures of Ag/SiO y /TiN and Ag/SiO x /TiN operate under either threshold switching or both modes. Insights regarding the impact of oxygen concentration into the conducting filament growth process are provided. The manifestation of the two switching modes permits the emulation of various synaptic effects, such as short-term plasticity and long-term plasticity whereas the modulation of the conductance values allows the synaptic weight tuning by controlling the amplitude or the frequency of the triggering signals. Moreover, arbitrary neuron characteristics were obtained from our volatile memory devices without integrating any other auxiliary circuit. Our approach provides valuable insights towards the realization of artificial neural networks from the same material configuration with biological-like dynamic behavior.

A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006

The SPEC CPU Benchmarks are used extensively for evaluating and comparing improvements to computer systems. This ubiquity makes characterization critical for researchers to understand the bottlenecks the benchmarks do and do not expose and where new designs should and should not be expected to show impact. However, in characterization there is a tradeoff between accuracy and reusability: The more precisely we characterize a benchmark’s performance on a given system, the less usable it is across different micro-architectures and varying memory configurations. For SPEC, most existing characterizations include system-specific effects (e.g., via performance counters) and/or only look at aggregate behavior (e.g., averages over the full application execution). While such approaches simplify characterization, they make it difficult to separate the applications’ intrinsic behavior from the system-specific effects and/or lose the diverse phase-based behaviors. In this work we focus on characterizing the applications’ intrinsic memory behaviour by isolating them from micro-architectural configuration specifics. We do this by providing a simplified generic system model that evaluates the applications’ memory behavior across multiple cache sizes, with and without prefetching, and over time. The resulting characterization can be reused across a range of systems to understand application behavior and allow us to see how frequently different behaviors occur. We use this approach to compare the SPEC 2006 and 2017 suites, providing insight into their memory system behaviour beyond previous system-specific and/or aggregate results. We demonstrate the ability to use this characterization in different contexts by showing a portion of the SPEC 2017 benchmark suite that could benefit from giga-scale caches, despite aggregate results indicating otherwise.

MespaConfig: Memory-Sparing Configuration Auto-Tuning for Co-Located In-Memory Cluster Computing Jobs

Distributed in-memory computing frameworks usually have lots of parameters (e.g., the buffer size of shuffle) to form a configuration for each execution. A well-tuned configuration can bring large improvements of performance. However, to improve resource utilization, jobs are often share the same cluster, which causes dynamic cluster load conditions. According to our observation, the variation of cluster load reduces effectiveness of configuration tuning. Besides, as a common problem of cluster computing jobs, overestimation of resources also occurs during configuration tuning. It is challenging to efficiently find the optimal configuration in a shared cluster with the consideration of memory-sparing. In this article, we introduce MespaConfig, a job-level configuration optimizer for distributed in-memory computing jobs. Advancements of MespaConfig over previous work are features including memory-sparing and load-sensitive. We evaluate MespaConfig by 6 typical Spark programs under different load conditions. The evaluation results show that MespaConfig improves the performance of six typical programs by up to 12× compared with default configurations. MespaConfig also achieves at most 41 percent reduction of configuration memory usage and reduces the optimization time overhead by 10.8× compared with the state-of-the-art approach.

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.

Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

Associative recognition memory for identity, spatial and temporal relations in healthy aging

ABSTRACT The ability to generate associative representations and to retrieve them from long-term episodic memory generally declines in healthy aging. However, it is unclear whether healthy aging has differential effects on associative memory for identity, spatial configuration, and temporal order relationships. In the current study, we assessed how healthy aging impacts on associative memory for identity, spatial, or temporal relationships between pairs of visual objects via discrimination of intact and rearranged pairs. Accuracy and response time performance of healthy older adults (aged 65–80) were compared with young adults (ages 19–30). Age-related declines in associative memory were observed equally for all types of associations, but these declines differed by associative status: aging most strongly affected ability to discriminate rearranged pairs. These results suggest that associative memory for identity, spatial, and temporal relationships are equally affected by healthy aging, and may all depend on a shared set of basic associative mechanisms.

A memória da ditadura em dois romances latino-americanos: a loucura e a glória

O objetivo principal deste artigo é apresentar uma discussão acerca da constituição da memória e dos possíveis significados evocados pelos relatos e pelas lembranças dos narradores-personagens nos romances Bêbados e sonâmbulos (1996) de Bernardo Carvalho e Duas vezes junho (2005) de Martín Kohan. Nesta análise, a loucura e a falsa glória, respectivamente, de contextos de governos militares no Brasil e na Argentina apresentam-se como temas contrastantes e, ao mesmo tempo, convergentes no que tange aos efeitos resultantes da configuração estética da memória em ambas narrativas. Deste modo, serão utilizadas, dentre outras, as concepções de Henry Bergson (1999) e Beatriz Sarlo (2005) sobre memória; de Maria José Rezende (2001) e Luis Alberto Romero (2012) sobre a reflexão historiográfica e filosófica dos contextos de ditaduras militares no Brasil e na Argentina, a fim de observar como se dá a estética da memória nos romances propostos para análise.

Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform

In the present age of high-density integrated circuits, radiation-induced adjacent multibit upsets (AMBUs) or clustered errors are very prominent in the configuration memory of static-random-access-memory-based field-programmable gate array (FPGA) devices. Radiated particles with high energy and low momentum may damage a group of adjacent logic cells and switches in reconfigurable devices, which can lead to clustered errors. Commonly used error mitigation techniques in the FPGA either have large overheads, complex decoding circuitry, or are not very efficient to correct AMBUs. Hence, efficient multibit error-correcting codes with low redundancy are of utmost need to mitigate the effect of AMBUs. Configuration data of the FPGAs are composed of a number of configuration frames (CFs), and there is a high probability that multiple physically adjacent CFs may be affected by clustered error. Hence, interleaving among CFs is quite advantageous for mitigation of clustered errors in the configuration memory of the FPGA. In this article, we have proposed a simple and efficient error mitigation model combining Hamming product code (HPC) with frame interleaving and selective bit placement, termed as “HPCFISBP” to correct AMBUs in the configuration memory of the FPGA without any modification in its basic architecture. The HPCFISBP provides better bit error rate performance nearly by 20 and 10 dB compared to Hamming code and HPC, respectively. The enhanced performance of the HPCFISBP has also been established through comparison with the state-of-the-art techniques in terms of error correction coverage, error correction time, redundancy, and residual error.