Channel Memory Research Articles

Implementation problems of high-speed DDR4 channels in a new generation Russian multi-core microprocessor

Solving the issue of compatibility for the new domestic developments with continuously implemented and used in global microelectronics industry cutting-edge standards requires substantial work on analysis and optimization of the implementation environment. The results of the new Elbrus 8SV microprocessor DDR4 random access memory channel study are provided in this article. The much lower than estimated channel data transfer speed has become the main issue. In order to overcome it the channel functioning study method has been developed and implemented. It is based on forming the analogs of eye diagrams, which allow estimating the area of operability and using the optimal settings. Studies held using this method allowed establishing the cause for unsatisfactory performance of the channel and objectively assessing design decisions made during development. After taking these results into account and applying changes to the chip and the circuit board of the microprocessor case, an improved version of the microprocessor was released. It became possible to achieve the calculated data transfer speed via the memory channel.

Channel Equalization With Expectation Propagation at Smoothing Level

In this paper we propose a novel turbo equalizer based on the expectation propagation (EP) algorithm. Optimal equalization is computationally unfeasible when high-order modulations and/or large memory channels are used. In these scenarios, low-cost and suboptimal equalizers, such as those based on the linear minimum mean square error (LMMSE), are commonly used. The LMMSE-based equalizer can be efficiently implemented with a Kalman smoother (KS), i.e., a forward and backward Kalman filtering whose predictions are merged in a posterior smoothing step. Recently, it was shown that applying EP at the forward and backward stages of a KS equalizer could significantly improve its performance. In this paper, we investigate applying EP at the smoothing level instead. Also, we propose some further modifications to better exploit the information coming from the channel decoder in turbo equalization schemes. Overall, we remarkably reduce the computational complexity while highly improving the performance in terms of bit error rate.

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems

A modern memory system is equipped with many memory channels to obtain a high memory bandwidth. To take the advantage of this organization, applications’ data are distributed among the channels and transferred in an interleaved fashion. Although memory-intensive applications benefit from a high bandwidth by many memory channels, applications such as compute-intensive ones do not need the high bandwidth. To reduce the energy consumption for such applications, the memory system has low-power modes. During no memory request, the main memory can enter these modes and reduce energy consumption. However, these applications often cause intermittent memory requests to the channels that handle their data, resulting in not entering the low-power modes. Hence, the memory system cannot enter the low-power modes even though the applications do not need the high bandwidth. To solve this problem, this paper proposes a dynamic data allocation mechanism for many-channel memory systems. This mechanism forces data of such applications to use the specified channels by dynamically changing the address-mapping schemes and migrating the data. As a result, the other channels to which the data are not allocated can have a chance to enter the low-power modes for a long time. Therefore, the proposed mechanism has the potential to reduce the energy consumption of many-channel memory systems. The evaluation results show that this mechanism can reduce the energy consumption by up to 11.8% and 1.7% on average.

Delay in Cooperative Communications: Achieving Higher Multiplexing Gain in Gaussian Interference Channels With Full-Duplex Transmitters

Delay, guaranteeing causality, is inevitable in cooperative communication systems. Traditionally, delay granularity has been limited to one symbol; however, channel delay is in fact governed by channel memory and can be shorter. For example, the delay requirement in orthogonal frequency-division multiplexing, captured in the cyclic prefix, is typically much shorter than the symbol itself. This perspective is used to study the two-user Gaussian interference channel with full-duplex transmitters. By superimposing the signal from the other node onto its own signal, each transmitter cancels the interference at its receiver. Among other results, it is proved that under a mild condition, the maximum multiplexing gain of this channel is in fact two, rather than the limit of one, previously shown under the traditional constraint of causal delay. Further, the optimal power allocation among orthogonal sub-carriers, which maximizes the achievable sum-rate, is shown to be a generalization of the well-known water filling. Simulation results are included to demonstrate the improvement in the achievable sum-rate when full-duplex transmitters are used.

Quantum link bootstrapping using a RuleSet-based communication protocol

Establishing end-to-end quantum connections requires quantified link characteristics, and operations need to coordinate decision-making between nodes across a network. We introduce the RuleSet-based communication protocol for supporting quantum operations over distant nodes to minimize classical packet transmissions for guaranteeing synchronicity. RuleSets are distributed to nodes along a path at connection set up time, and hold lists of operations that need to be performed in real time. We simulate the RuleSet-based quantum link bootstrapping protocol, which consists of recurrent purifications and link-level tomography, to quantify the quantum link fidelity and its throughput. Our Markov-Chain Monte-Carlo simulation includes various error sources, such as the memory error, gate error and channel error, modeled on currently available hardware. We found that when two quantum nodes, each with 100 memory qubits capable of emitting photons ideally to the optical fiber, are physically connected with a 10km MeetInTheMiddle link, the Recurrent Single selection - Single error purification (RSs-Sp) protocol is capable of bringing up the fidelity from an average input $F_{r}=0.675$ to around $F_{r}=0.865$ with a generation rate of 1106 Bell pairs per second, as determined by simulated tomography. The system gets noisier with longer channels, in which case errors may develop faster than the purification gain. In such a situation, a stronger purification method, such as the double selection-based purification, shows an advantage for improving the fidelity. The knowledge acquired from bootstrapping can later be distributed to nodes within the same network, and used for other purposes such as route selection.

Noninvasive Brain Stimulation Enhances Memory Acquisition and Is Associated with Synaptoneurosome Modification in the Rat Hippocampus.

Transcranial direct-current stimulation (tDCS) is a non-invasive brain stimulation approach previously shown to enhance memory acquisition, but more studies are needed to elucidate the underlying mechanisms. Here, we examined the effects of anodal tDCS (0.25 mA for 30 min) on the memory performance of male Sprague Dawley rats in the passive avoidance test (PAT) and the associated modifications to the hippocampal proteomes. Results indicate anodal tDCS applied before the acquisition period significantly enhanced memory performance in the PAT. Following PAT, synaptoneurosomes were biochemically purified from the hippocampi of tDCS-treated or sham-treated rats and individual protein abundances were determined by bottom-up liquid chromatography mass spectrometry analysis. Proteomic analysis identified 184 differentially expressed hippocampal proteins when comparing the sham to the tDCS before memory acquisition treatment group. Ingenuity pathway analysis (IPA) showed anodal tDCS before memory acquisition significantly enhanced pathways associated with memory, cognition, learning, transmission, neuritogenesis, and long-term potentiation (LTP). IPA identified significant upstream regulators including bdnf, shank3, and gsk3b. Protein-protein interaction (PPI) and protein sequence similarity (PSS) networks show that glutamate receptor pathways, ion channel activity, memory, learning, cognition, and long-term memory were significantly associated with anodal tDCS. Centrality measures from both networks identified key proteins including dlg, shank, grin, and gria that were significantly modified by tDCS applied before the acquisition period. Together, our results provide descriptive molecular evidence that anodal tDCS enhances memory performance in the PAT by modifying hippocampal synaptic plasticity related proteins.

Remembering the Blister: How What Didn't Kill Me Made Me Stronger

I'm an ethnographer at a major financial institution. My work became a lot more meaningful after my family and I lost our home in a devastating arson attack. In this Pecha Kucha, I tell the story of how this catastrophic fire loss forced me to reclaim my agency. Today, I channel memories of bereavement and recovery into my quest to improve experiences for customers and in my community. “Knowledge is awareness that fire can burn; wisdom is remembering the blister.” —Leo Tolstoy

Union Bound Analysis and Code Design for Multilevel Flash Memory Channels

Multilevel flash memories enable multiple bits to be stored in a single memory cell and hence a significant increase of the storage capacity. The multiple bits that are used for labeling the threshold voltage level of a memory cell belong to different pages. A multilevel flash memory channel resembles a multi-user channel with asymmetric noise, while the data of different pages, which are encoded independently, resembles data of multiple users. In this paper, performance analyses are proposed for this channel by using the union bound technique. In particular, we investigated two different binary labeling schemes of a cell level, the Gray labeling and non-Gray labeling with three maximum-likelihood (ML)-based decoding schemes, which are the joint multi-page ML decoding, page-separate ML decoding, and default setting ML decoding. Our analysis reveals an asymptotic diminishing rate of decoding errors as the channel noise approaches zero, based on which the code design criteria are proposed. It is shown theoretically that the Gray mapping has no joint (i.e., multi-page) decoding gain. The corresponding diminishing decoding error rate is dominated by the weakest code in each page and hence a separate decoding scheme is adequate. On the other hand, the non-Gray mapping has a joint decoding gain which means the weak code can exploit the decoding of the strong code and the diminishing rate of its decoding errors is not subject to the cask effect. Therefore, for Gray mapping, a symmetric coding scheme using equal-strength code for each page achieves better error performance, while for non-Gray mapping with joint decoding, the symmetric coding is not necessary. Moreover, by using the asymmetric coding scheme through assigning different code rates to different pages, the non-Gray mapping can achieve higher overall sum rate than Gray mapping with a similar decoding error rate performance.

Development of memory controller for today’s Elbrus microprocessors

The introduction of a new generation of microprocessors that belong to the Elbrus family and involve the introduction of a network-on-chip, requires the development of efficient means of access to DDR random access memory channels for network nodes. The paper includes a solution to this issue related to the interaction between DDR4 RAM and Elbrus-16СВ, 16-core microprocessor, which demands higher standards of an available capacity and peak bandwidth of memory channels. When designing Elbrus-16CB microprocessor, higher energy efficiency and reliability are also between main objectives. When performing the tasks set, an important component was adaptation of the memory controller, successfully applied in the microprocessors produced by MCST JSC, to DDR4 3DS standard compliance, taken as a basis for the use in a number of recent developments. It provides a four-time higher available RAM capacity without a directly proportional growth of energy consumption. The paper includes a structure of the memory controller and made decisions. These make it possible to increase the target frequency in operations of the device by 30% up to 800 MHz and increase operation reliability of the memory channel.

Deep Learning-Aided Dynamic Read Thresholds Design for Multi-Level-Cell Flash Memories

The practical NAND flash memory suffers from various non-stationary noises that are difficult to be predicted. For example, the data retention noise induced channel offset is unknown during the readback process, and hence severely affects the reliability of data recovery from the memory cell. In this paper, we first propose a novel recurrent neural network (RNN)-based detector to effectively detect the data stored in the multi-level-cell (MLC) flash memory without the prior knowledge of the channel. However, compared with the conventional threshold detector, the proposed RNN detector introduces much longer read latency and more power consumption. To tackle this problem, we further propose an RNN-aided (RNNA) dynamic threshold detector, whose detection thresholds can be derived based on the outputs of the RNN detector. We thus only need to activate the RNN detector periodically when the system is idle. Moreover, to enable soft-decision decoding of error-correction codes, we first show how to obtain more read thresholds based on the hard-decision read thresholds derived from the RNN detector. We then propose integer-based reliability mappings based on the designed read thresholds, which can generate the soft information of the channel. Finally, we propose to apply density evolution (DE) combined with the differential evolution algorithm to optimize the read thresholds for low-density parity-check (LDPC) coded flash memory channels. Computer simulation results demonstrate the effectiveness of our proposed RNNA dynamic read thresholds design, for both the uncoded and LDPC-coded flash memory channels, without any prior knowledge of the channel.

Low-Cost 1-$\mu$ m Photolithography Technologies for Large-Body-Size, Low-Resistance Panel-Based RDL

This paper presents the latest advances in photolithography technologies to enable scaling of package redistribution layer (RDL) toward critical dimensions (CD) of $1 ~\mu \text{m}$ and below. High-bandwidth memory channels require not only fine pitch but also low-trace-delay RDL. High-aspect-ratio (AR) traces enable lower delays, and the photolithographic advances to achieve such traces are demonstrated on panel-based glass substrates for packages with low cost, high input/output (I/O) density, high bandwidth, and large body size. CD of 0.9- $\mu \text{m}$ line and space with an AR of 5.5 was successfully demonstrated using a low-numerical aperture (NA = 0.16) $1 \times$ i-line projection stepper tool with a novel chemically amplified plating photoresist. The 1- $\mu \text{m}$ lithography technology is a must for high-density RDL to enable 2.5-D interposer and embedded fan-out package substrates. These architectures can achieve I/O densities of 500 IOs/mm/layer. The resistance of the trace with an AR of 5 is five times lower than a trace with an AR of 1. This technological advance will greatly reduce the signal propagation loss and increase the data rate of the RDL traces. The combination of high density and high data rate will greatly increase the system interconnect bandwidth. Furthermore, low-NA stepper with a large exposure area will enable the fabrication of large-body-size interposers at low cost. This paper analyzes the relationship between trace width resolution ( $w$ ), depth of focus, and materials to conclude that it is feasible to fill the gap between semiconductor back-end-of-line and package substrate RDL technologies. The final section discusses the issues in process development of lithography for multilayer fine-line RDLs.

Every entangled state provides an advantage in classical communication

We investigate the use of noisy entanglement as a resource in classical communication via a quantum channel. In particular, we are interested in the question whether for any entangled state, including bound entangled states, there exists a quantum channel, the classical capacity of which can be increased by providing the state as an additional resource. We partially answer this question by showing, for any entangled state, the existence of a quantum memory channel, the feedback-assisted classical capacity with product encodings of which can be increased by using the state as a resource. Using a different (memoryless) channel construction, we also provide a sufficient entropic condition for an advantage in classical communication (without feedback and for general encodings) and thus provide an example of a state that is not distillable by means of one-way local operations and classical communication but can provide an advantage in the classical capacity of a number of quantum channels. As separable states cannot provide an advantage in classical communication, our condition also provides an entropic entanglement witness.

A Novel Dynamic Detection for Flash Memory

The incorporation of powerful soft-decision error correction codes (e.g., LDPC) to replace legacy hard-decision codes (e.g., BCH) can boost the reliability of flash memory beyond its current limits at the expense of additional reading latency to generate soft information, namely in the form of log-likelihood ratios (LLRs). Unfortunately, the memory channel varies significantly depending on several factors (e.g., temperature, parasitic coupling, and retention time) which renders the use of precomputed LLR lookup table (LUT) ineffective especially as the device ages. In fact, the estimated LLRs need to be regularly updated to avoid any performance degradation. We provide a dynamic yet low-latency blind detection algorithm which is able to adaptively adjust the hard/soft-decision boundaries and estimate the corresponding LLR codebook. The proposed demodulator offers near-optimal performance with low-complexity overhead.

Improving adaptive receivers performance in molecular communication via diffusion.

Forthcoming applications for molecular communications (MC) such as drug-delivery and health monitoring will require robust receiver capabilities to mitigate channel memory and inter symbol interference caused by previous transmitted symbols. Here, the authors introduce an adaptive weighted algorithm to reduce the influence of these factors. This novel signal detection is deployed on to a concentration-based MC system with absorbing receiver which is based on the so-called first passage time concept. The proposed detector has low complexity and does not require explicit channel knowledge. To evaluate authors' proposed algorithm, a theoretical approach is developed to derive the bit error rate (BER). Numerical results also carried out to verify the accuracy of these formulations and establish that the new detector will achieve better performance in comparison with other common low-complex detectors under certain scenarios. Additionally, the authors propose a simple pre-coding technique to combat the sequence of consecutive ones in low ISI scenarios. Also a comparison between detectors is given, which is based on the variation of distance, symbol period, signal-to-noise ratio (SNR), and number of molecules.

Comparison of Wideband Interconnecting Technologies for Multigigahertz Novel Memory Architecture

Recently proposed multicarrier memory channel architecture [1], [2] pioneered the use of substrate integrated waveguide (SIW) as a viable high-bandwidth interconnect in memory channels. In this paper, we validate the merit of our proposal by comparing it with a leading transmission-line-based bandpass filter (TLBPF). We show that in X-band that the SIW interconnect achieves more than two times higher bandwidth than TLBPF. TLBPF suffers from the impact of conductive attenuation, which causes the outer symbols to drift in toward the center of the constellation diagram and results in an abrupt degradation in bit error rate (BER). The cumulative effects of such impairments cause TLBPF-based platform to saturate at 200-MHz rate (2400 Mb/s). In contrast, SIW-based platform achieves 400-MHz transfer rate (4800 Mb/s) without equalization and/or signal recovery algorithms while preserving a BER smaller than 3.0e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and an error vector magnitude less than 9.7%.

Quantum Correlation in Squeezed Generalized Amplitude Damping Channels with Memory

A squeezed generalized amplitude damping (SGAD) channel is a quantum channel that models a general noise process incorporating the effects of bath squeezing, dissipation, and decoherence. In this paper, we analyze the dynamics of quantum entanglement and discord in the SGAD channel with memory. By obtaining a stochastic map defining this noisy quantum channel, we derive the concurrence and discord of Werner-like mixed states sent by successive uses of the channel. It is shown that these quantum correlations can be preserved or even generated depending on the initial channel input states, channel parameters, and the degree of channel memory. In particular, the squeezing effect does not contribute to the dynamics of quantum correlation for singlet-like states under correlated noise.

Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and 25 Ω and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.

Discrimination between two memory channels by molecular alloying in a doubly bistable spin crossover material.

A multistable spin crossover (SCO) molecular alloy system [Fe1-x M x (nBu-im)3(tren)](P1-y As y F6)2 (M = ZnII, NiII; (nBu-im)3(tren) = tris(n-butyl-imidazol(2-ethylamino))amine) has been synthesized and characterized. By controlling the composition of this isomorphous series, two cooperative thermally induced SCO events featuring distinct critical temperatures (T c) and hysteresis widths (ΔT c, memory) can be selected at will. The pristine derivative 100As (x = 0, y = 1) displays a strong cooperative two-step SCO and two reversible structural phase transitions (PTs). The low temperature PTLT and the SCO occur synchronously involving conformational changes of the ligand's n-butyl arms and two different arrangements of the AsF6 - anions [T1c = 174 K (ΔT1c = 17 K), T2c = 191 K (ΔT2c = 23 K) (scan rate 2 K min-1)]. The high-temperature PTHT takes place in the high-spin state domain and essentially involves rearrangement of the AsF6 - anions [TPTc = 275 K (ΔTPTc = 16 K)]. This behavior strongly contrasts with that of the homologous 100P [x = 0, y = 0] derivative where two separate cooperative one-step SCO can be selected by controlling the kinetics of the coupled PTLT at ambient pressure: (i) one at low temperatures, T c = 122 K (ΔT c = 9 K), for temperature scan rates (>1 K min-1) (memory channel A) where the structural modifications associated with PTLS are inhibited; (ii) the other centered at T c = 155 K (ΔT c = 41 K) for slower temperature scan rates ≤0.1 K min-1 (memory channel B). These two SCO regimes of the 100P derivative transform reversibly into the two-step SCO of 100As upon application of hydrostatic pressure (ca. 0.1 GPa) denoting the subtle effect of internal chemical pressure on the SCO behavior. Precise control of AsF6 - ↔ PF6 - substitution, and hence of the PTLT kinetics, selectively selects the memory channel B of 100P when x = 0 and y ≈ 0.7. Meanwhile, substitution of FeII with ZnII or NiII [x ≈ 0.2, y = 0] favors the low temperature memory channel A at any scan rate. This intriguing interplay between PT, SCO and isomorphous substitution was monitored by single crystal and powder X-ray diffractometries, and magnetic and calorimetric measurements.

Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories

A protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) code for multi-level cell (MLC) NAND flash memories is proposed in this paper. In this design approach, the quantized voltage signals are measured for soft decoding because the exact voltage values are unavailable. Flash memory channels are asymmetric, and therefore, not optimal for existing LDPC codes optimized for symmetric additive white Gaussian noise (AWGN)-like channels. Mutual information (MI) between the input and output of flash memory is used to model the quantized log-likelihood ratio (LLR) messages. The base matrix of the method is constructed according to the degree sequences optimized by the modified extrinsic information transfer (EXIT) chart method for flash memories. The designed protograph-based codes have a low-complexity QC encoder structure with a readily parallelizable decoder structure. In addition, rate-adaptive polar code design based on Bhattacharyya parameters of the memory cell bits is proposed to further improve the storage efficiency of the MLC NAND flash memories. The code design takes advantage of the inherent characteristics of MLC flash memory channel to iteratively calculate the Bhattacharyya parameter of each memory cell bit, where the punctured positions are selected by choosing the bits with higher Bhattacharyya parameters to construct rate-adaptive polar codes. The simulation results confirm the benefits of the proposed coding schemes.

Security-Enhanced SC-FDMA Transmissions Using Temporal Artificial-Noise and Secret Key Aided Schemes

We investigate the physical-layer security of uplink single-carrier frequency-division multiple-access (SC-FDMA) systems. Multiple users, Alices, send confidential messages to a common legitimate base-station, Bob, in the presence of an eavesdropper, Eve. To secure the legitimate transmissions, each user superimposes an artificial noise (AN) signal on the time-domain SC-FDMA data symbol. We reduce the computational and storage requirements at Bob's receiver by assuming simple per-sub-channel detectors. We assume that Eve has global channel knowledge of all links in addition to high computational capabilities, where she adopts high-complexity detectors such as single-user maximum likelihood (ML), multi-user minimum-mean-square-error, and multi-user ML. We analyze the correlation properties of the time-domain AN signal and illustrate how Eve can exploit them to reduce the AN effects. We prove that the number of useful AN streams that can degrade Eve's signal-to-noise ratio is dependent on the channel memories of Alices-Bob and Alices-Eve links. Furthermore, we enhance the system security for the case of partial Alices-Bob channel knowledge at Eve, where Eve only knows the precoding matrices of the data and AN signals instead of knowing the entire Alices-Bob channel matrices, and propose a hybrid security scheme that integrates temporal AN with channel-based secret key extraction.