Implementation problems of high-speed DDR4 channels in a new generation Russian multi-core microprocessor

Abstract

Solving the issue of compatibility for the new domestic developments with continuously implemented and used in global microelectronics industry cutting-edge standards requires substantial work on analysis and optimization of the implementation environment. The results of the new Elbrus 8SV microprocessor DDR4 random access memory channel study are provided in this article. The much lower than estimated channel data transfer speed has become the main issue. In order to overcome it the channel functioning study method has been developed and implemented. It is based on forming the analogs of eye diagrams, which allow estimating the area of operability and using the optimal settings. Studies held using this method allowed establishing the cause for unsatisfactory performance of the channel and objectively assessing design decisions made during development. After taking these results into account and applying changes to the chip and the circuit board of the microprocessor case, an improved version of the microprocessor was released. It became possible to achieve the calculated data transfer speed via the memory channel.