Channel Memory Research Articles

GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks

Graph Neural Network (GNN) models have attracted attention, given their high accuracy in interpreting graph data. One of the primary building blocks of a GNN model is aggregation, which gathers and averages the feature vectors corresponding to the nodes adjacent to each node. Aggregation works by multiplying the adjacency and feature matrices. The size of both matrices exceeds the on-chip cache capacity for many realistic datasets, and the adjacency matrix is highly sparse. These characteristics lead to little data reuse, causing intensive main-memory accesses during the aggregation process. Thus, aggregation exhibits memory-intensive characteristics and dominates most of the total execution time. In this paper, we propose GraNDe, an NDP architecture that accelerates memory-intensive aggregation operations by locating NDP modules near DRAM datapath to exploit rank-level parallelism. GraNDe maximizes bandwidth utilization by separating the memory channel path with the buffer chip in between so that pre-/post-processing in the host processor and reduction in NDP modules operate simultaneously. By exploring the preferred data mappings of the operand matrices to DRAM ranks, we architect GraNDe to support adaptive matrix mapping that applies the optimal mapping for each layer depending on the dimension of the layer and the configuration of a memory system. We also propose adj-bundle broadcasting and re-tiling optimizations to reduce the transfer time for adjacency matrix data and to improve feature vector data reusability by exploiting tiling with consideration of adjacency between nodes. GraNDe achieves 3.01× and 1.69× on average, and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$4.00\times$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1.98\times$</tex-math></inline-formula> speedups of GCN aggregation over the baseline system and the state-of-the-art NDP architecture for GCN, respectively.

Fraud Detection Based on Credit Review Texts with Dual Channel Memory Networks

ABSTRACT With the rapid development of the automotive finance market in China, fraudulent behaviors present new characteristics such as intellectualization and high concealment. Graph neural networks and memory networks have strong capabilities for processing the textual data containing massive complex associations, providing a new perspective for fraud detection. During the operation of an automotive finance company, a large amount of credit review texts with recording the customers’ multidimensional data are accumulated. These texts contain information that is helpful for risk management, but have not been well explored. In order to effectively identify fraud risks, we propose a fraud detection method based on credit review texts with dual-channel memory network, which combines graph and text memory networks. By utilizing pre-trained language models, the text data for credit review text is encoded into semantic vectors. The graph memory network module and the text memory network module are then employed to extract graph features and text features corresponding to the credit review text. Finally, the generated results from the three modules are fused and input into a classification network to obtain the final determination of financial fraud risk. Comparative experiments with baseline models demonstrate the validity of our model in fraud detection.

NeuroTAP: Thermal and Memory Access Pattern-aware Data Mapping on 3D DRAM for Maximizing DNN Performance

Deep neural networks (DNNs) have been widely adopted, owing to break-through performance and high accuracy. DNNs exhibit varying memory behavior involving specific and recognizable memory access patterns and access intensity, depending on the selected data reuse in different layers. Such applications have high memory bandwidth demands due to aggressive computations, performing several billion-floating-point-operations-per-second (BFLOPs). 3D DRAMs, providing very high memory access bandwidth, are extensively employed to break the memory wall , bridging the gap between compute and memory while running DNNs. However, the vertical integration in 3D DRAM introduces serious thermal issues, resulting from high power density and close proximity of memory cells, and requires dynamic thermal management (DTM). To unleash the true potential of 3D DRAM and exploit the enormous bandwidth under thermal constraints, there is a need to intelligently map the DNN application’s data across memory channels, pseudo-channels, and banks, minimizing the effective memory latency and reducing the thermal-induced application slowdown. The specific memory access patterns exhibited by a DNN layer execution are crucial to determine a favourable data mapping method for 3D DRAM dies that potentially causes minimal thermal impact, and also maximize DRAM bandwidth utilization. In this work, we propose an application-aware and thermal-sensitive data mapping that intelligently assigns portions of the 3D DRAM to DNN layers, leveraging the knowledge about layer’s memory access patterns and minimizing DTM-induced performance overheads. Additionally, we also deploy a DRAM low-power states based DTM mechanism to keep the 3D DRAM within safe thermal limits. Using our proposal, we observe a performance improvement of 1% to 61%, and memory energy savings of 1% to 55% for popular deep neural networks over state-of-the-art DTM strategies while running DNN inference.

RECEPTION ALGORITHM AS A WHOLE WITH ELEMENT-BY-ELEMENT DECISION MAKING USING THE PHASE MODULATION METHOD

The article is aimed to provide reception algorithm as a whole with element-by-element decision making. It belongs to the group of decision, making algorithms with feedback. It is used to demodulate discrete signals that have passed through a memory channel. The study presents an example of signal processing of a binary phase modulator. This example shows processing features that are not obvious for considering of the mathematical formula that describes demodulation algorithm. Another algorithm was developed for a quadrature phase modulator as well. The noise immunity for additive gaussian noise was estimated by the numerical simulations. The same researches was carried out using an equalizer filter that suppresses channel memory effect. Simulation results were used as the base for the graphs of the error probability versus signal-to-noise ratio.

Thresholds for the distributed surface code in the presence of memory decoherence

In the search for scalable, fault-tolerant quantum computing, distributed quantum computers are promising candidates. These systems can be realized in large-scale quantum networks or condensed onto a single chip with closely situated nodes. We present a framework for numerical simulations of a memory channel using the distributed toric surface code, where each data qubit of the code is part of a separate node, and the error-detection performance depends on the quality of four-qubit Greenberger–Horne–Zeilinger (GHZ) states generated between the nodes. We quantitatively investigate the effect of memory decoherence and evaluate the advantage of GHZ creation protocols tailored to the level of decoherence. We do this by applying our framework for the particular case of color centers in diamond, employing models developed from experimental characterization of nitrogen-vacancy centers. For diamond color centers, coherence times during entanglement generation are orders of magnitude lower than coherence times of idling qubits. These coherence times represent a limiting factor for applications, but previous surface code simulations did not treat them as such. Introducing limiting coherence times as a prominent noise factor makes it imperative to integrate realistic operation times into simulations and incorporate strategies for operation scheduling. Our model predicts error probability thresholds for gate and measurement reduced by at least a factor of three compared to prior work with more idealized noise models. We also find a threshold of 4×102 in the ratio between the entanglement generation and the decoherence rates, setting a benchmark for experimental progress.

Blind channel evaluation using OFDM-FHSS technology

Pseudo-random tuning of the operating frequency (PRFC) is one of the effective methods of spectrum expansion, in which the signal occupies a frequency band significantly wider than the minimum required for transmitting information. Тhe operating frequency of the signal is hopped over a wide range of the frequency range allocated for communication in accordance with a pseudo-random code, known only on the receiving side and unknown to anyone trying to intercept a radio transmission or organize jamming. The main disadvantage of HFPR is the low data transfer rate. Therefore, recently there have been ideas of using the hopping method with broadband signals, for example OFDM-hopping where the frequency changes within a set of orthogonal carriers. This approach makes it possible to preserve the advantages of the frequency converter method, supplementing them with the ability to implement high-speed digital communications. The paper considers the situation when one OFDM symbol is transmitted in the time interval of one hop, formed without a prefix and postfix. In this case, the transmission signal in the time interval of one step was a set of sequentially transmitted complex samples of the OFDM symbol envelope. Samples of the OFDM symbol envelope, after they are generated during transmission in the OBPF block, must be sequentially transmitted over a communication channel whose properties are unknown. In the case when there is temporary dissipation of the energy of the transmitted signal in the channel (channel memory), during the sequential transmission of complex samples of the OFDM symbol envelope, due to temporary dissipation, each of the previous samples will have an interference effect on any transmitted sample at reception. Assuming that the channel parameters are constant over the analysis interval at the receiving location, it is necessary, with an unknown impulse response of the channel, to generate estimates of the OFDM symbol envelope samples, which, in order to solve the demodulation problem, must be subjected to the FFT calculation operation. The constancy of the channel parameters over the analysis interval allows us to solve the problem of estimating samples of the channel impulse response using blind identification based on the maximum likelihood method. In this case, it is necessary to use diversity reception and impose some non-burdensome restrictions on the statistical properties of the transmitted message. After solving the problem of identifying the impulse response of a channel with memory, the problem of estimating the components of the sample vector of the envelope of the received OFDM symbol is solved by the regularization method. Using the “reception “as a whole” with element-by-element assessment generation” (PCPFO) algorithm and using “assessment feedback” (EFE), minimization of the regularizing functional leads to the solution of a system of linear algebraic equations, the order of which is determined by the number of samples of the impulse response of the communication channel with memory. By modeling, the upper limit of noise immunity for receiving OFDM-QAM-4 signals was obtained with a Gaussian distribution of errors in estimating OFDM-symbol envelope samples. The proposed procedure for normalizing envelope samples after solving systems of linear equations eliminates the appearance of outliers characteristic of the generated noise sequence.

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash

3D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity1. However, the 3D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct Polar Code in NAND flash memory. This paper proposes a new Polar Code construction method called Dynamic Merge Monte Carlo(DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate(UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%.

Deep Transfer Learning-Based Detection for Flash Memory Channels

Deep Transfer Learning-Based Detection for Flash Memory Channels

ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip

The introduction of High Bandwidth Memory (HBM) to the FPGA chip makes it possible for an FPGA-based accelerator to leverage the huge memory bandwidth of HBM to improve its performance when implementing a specific algorithm, which is especially true for the Breadth-First Search (BFS) algorithm that demands a high bandwidth for accessing the graph data stored in memory. Different from traditional FPGA-DRAM platforms where memory bandwidth is the precious resource due to the limited DRAM channels, FPGA chips equipped with HBM have much higher memory bandwidths provided by the large quantities of HBM channels, but still a limited amount of logic (LUT, FF, and BRAM/URAM) resources. Therefore, the key to design a high-performance BFS accelerator on an HBM-enhanced FPGA chip is to efficiently use the logic resources to build as many as possible Processing Elements (PEs) and configure them flexibly to obtain as high as possible effective memory bandwidth that is useful to the algorithm from the HBM, rather than partially emphasizing the absolute memory bandwidth. To exploit as high as possible effective bandwidth from the HBM, ScalaBFS2 conducts BFS in graphs in a vertex-centric manner and proposes designs, including the independent module (HBM Reader) for memory accessing, multi-layer crossbar, and PEs that implement hybrid mode (i.e., capable of working in both push and pull modes) algorithm processing, to utilize the FPGA logic resources efficiently. Consequently, ScalaBFS2 is able to build up to 128 PEs on the XCU280 FPGA chip (produced with the 16 nm process and configured with two HBM2 stacks) of a Xilinx Alveo U280 board and achieves performance of 56.92 Giga Traversed Edges Per Second (GTEPS) by fully using its 32 HBM memory channels. Compared with the state-of-the-art graph processing system (i.e., ReGraph) built on top of the same board, ScalaBFS2 achieves 2.52x~4.40x performance speedups. Moreover, when compared with Gunrock running on an Nvidia A100 GPU that is produced with the 7 nm process and configured with five HBM2e stacks, ScalaBFS2 achieves 1.34x~2.40x speedups on absolute performance, and 7.35x~13.18x speedups on power efficiency.

Concatenated Nanopore DNA Codes.

In nanopore sequencers, single-stranded DNA molecules (or k-mers) enter a small opening in a membrane called a nanopore and modulate the ionic current through the pore, producing a channel output in the form of a noisy piecewise constant signal. An important problem in DNA-based data storage is finding a set of k-mers, i.e. a DNA code, that is robust against noisy sample duplication introduced by nanopore sequencers. Good DNA codes should contain as many k-mers as possible that produce distinguishable current signals (squiggles) as measured by the sequencer. The dissimilarity between squiggles can be estimated using a bound on their pairwise error probability, which is used as a metric for code design. Unfortunately, code construction using the union bound is limited to small k's due to the difficulty of finding maximum cliques in large graphs. In this paper, we construct large codes by concatenating codewords from a base code, thereby packing more information in a single strand while retaining the storage efficiency of the base code. To facilitate decoding, we include a circumfix in the base code to reduce the effect of the nanopore channel memory. We show that the decoding complexity scales as [Formula: see text], where m is the number of concatenated k-mers. Simulations show that the base code error rate is stable as m increases.

GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs

Recent advances in graph processing on FPGAs promise to alleviate performance bottlenecks with irregular memory access patterns. Such bottlenecks challenge performance for a growing number of important application areas like machine learning and data analytics. While FPGAs denote a promising solution through flexible memory hierarchies and massive parallelism, we argue that current graph processing accelerators either use the off-chip memory bandwidth inefficiently or do not scale well across memory channels. In this work, we propose GraphScale, a scalable graph processing framework for FPGAs. GraphScale combines multi-channel memory with asynchronous graph processing (i.e., for fast convergence on results) and a compressed graph representation (i.e., for efficient usage of memory bandwidth and reduced memory footprint). GraphScale solves common graph problems like breadth-first search, PageRank, and weakly connected components through modular user-defined functions, a novel two-dimensional partitioning scheme, and a high-performance two-level crossbar design. Additionally, we extend GraphScale to scale to modern high-bandwidth memory (HBM) and reduce partitioning overhead of large graphs with binary packing.

CHOICE OF CODE FOR DETECTING ERRORS IN BACKUP CHANNELS OF A DUPLICATED COMPUTER

An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of aerospace equipment was carried out. The requirements for the methods of redundant computer systems are formulated. A comparative evaluation of the detecting ability and hardware costs in the implementation of the majority method of redundancy, the method of duplication and the use of corrective codes is carried out. The expediency of using the duplication method to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes, to identify a faulty backup channel is substantiated. Unlike the known codes, it is proposed to use an algebraic linear code, in which the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical operation of inverting required to represent a negative number in an additional code, which makes it possible to adapt the code to control the arithmetic and logical operations of the computer processor. The evaluation of the probability of failure-free operation of a duplicated computer, with its general redundancy, with the detection and correction of single errors in the backup memory channels and the detection of errors in the backup channels of the processor ALU based on the proposed code, and the assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. As a result of comparing the probabilities of failure-free operation, it has been established that the total reservation of the computer based on the proposed code, in comparison with the separate reservation of the memory and ALU of the processor of the computer, makes it possible to provide a gain in the probability of failure-free operation of the computer and its functional units throughout the entire period of operation.

Use of information redundancy to increase the reliability of devices for storing, processing and transmitting information

In modern information transmission systems, a special place is occupied by telecommunication systems (TS), which include digital data transmission systems (DSTS) containing specialized computers (SEVMs). The systems under consideration must ensure fast and reliable transmission of discrete data over communication lines. In this case, the loss of even one transmitted character is unacceptable; therefore, the main indicator of the reliability of a computer is the probability of failure-free operation. To increase the probability of failure-free operation of a storage device (MS), corrective codes and duplication are used, and to increase the probability of failure-free operation of the arithmetic-logical unit (ALU) of a computer, majority redundancy is used. The disadvantage of the majority method is the high hardware costs for redundancy, which reduces the efficiency of its use. The disadvantages of using correction codes include: as a rule, they are used for separate redundancy (detection and correction of errors that occur in storage devices; majority redundancy is used to detect and correct errors in the ALU); not all arithmetic and logical operations can be controlled based on existing correcting codes; a sharp increase in hardware costs when using algebraic linear codes to detect and correct multiple errors. Detection of errors in the ALU of a computer processor can be achieved on the basis of duplication in a loaded mode with replacement, however, this is associated with solving the main problem of computer duplication: - selection of monitoring tools for determining a failed channel (detection of errors in storage and information processing devices). The purpose of the research is to develop a scientific and methodological apparatus for computer backup using the duplication method with error detection in backup channels based on the use of an algebraic linear code, which makes it possible to detect errors not only in storage devices, but also adapted for detecting errors when performing arithmetic and logical operations. Results. An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of telecommunication systems was carried out. Requirements for computer backup methods are formulated. A comparative assessment of the detecting ability and hardware costs was carried out when implementing the majority redundancy method, the duplication method and the use of correcting codes. The expediency of using the duplication method is substantiated to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes to determine the faulty channel, which allows to significantly reduce hardware costs for constructing monitoring equipment and use 10-30% of backup equipment for these purposes. It is proposed to use an algebraic linear code, in which, unlike well-known codes, the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical inversion operation , necessary to represent a negative number in two's complement code, which makes it possible to adapt the code to control arithmetic and logical operations of the computer processor. An assessment was made of the probability of failure-free operation of a duplicated computer, with its general redundancy, with detection and correction of single errors in the backup memory channels and detection of errors in the backup channels of the processor ALU based on the proposed code, and an assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. A comparative assessment of the probabilities of failure-free operation allows us to conclude that the general redundancy of the computer based on the proposed code, in comparison with the separate redundancy of the memory and ALU of the computer processor, allows for a gain in the probability of failure-free operation of the computer and its functional devices throughout the entire period of operation. The practical significance lies in the fact that the proposed scientific and methodological apparatus provides: reduction of hardware costs for identifying a faulty channel when organizing duplication; detection of errors in the memory and ALU of the computer processor with time costs not exceeding the time of error detection when using standard methods of monitoring the computer system.

The use of OFDM signals in pseudorandom tuning of the operating frequency technology (FHSS)

The paper investigates the ways of organizing FHSS communication system using OFDM signals under the conditions of the measured parameters of the channel used. It is assumed that "protective gaps" are not used in the structure of the group signal FHSS technology. A variant of the formation of the OFDM symbol structure with a "test combination" is considered, the knowledge of which allows the regularization method to solve the problem of estimating the samples of the impulse response of the communication channel with memory. In this case, estimates are obtained from solving a system of algebraic equations, the order of which is determined by the size of the channel memory. To solve the problem of demodulating the signal from the "working package" of the OFDM symbol, estimates of the envelope counts of this part of the OFDM symbol are formed, according to which decisions on the transmitted discrete symbols are recorded at the output of the FFT calculation unit. Data on computer modeling of the problems under consideration are presented, the results of which confirm the possibility of using the proposed solutions for special purpose networks.

Channels of Memory about the USSR for “Generation X”: from Post-Soviet Media Interpretations to Family Experience

They are called “Generation X”, their childhood and youth fell in the 1980s, they had their own access to the Soviet reality, being, as a rule, in the bosom of the family. Reading the texts of newspapers, analyzing the content of post-Soviet TV projects, the author tries to answer the question, whether these interpretations and broadcasts of images of the Soviet Union correspond to the own impressions of representatives of “Generation X”, for which the ideas of A. Assmann, M. Hirsch, G. Harman, A. Yurchak, as well as interviews of actors of different generations are involved. It is concluded that today, under the influence of the media, at one time, young witnesses of the USSR formed a special — divided — perception of the Soviet past.

Algorithm for capacity estimation based on time resolution theory with linear computational complexity for frequency-selective communication channels and PAM-n-signals

Problem statement. At that moment, it is relevant to create algorithms for communication channels capacity estimation within the framework of the Theory of Resolution Time for broadband wired telecommunication systems, which use bipolar PAM-n-signal whose execution time complexity is linear. The creation of such algorithms is of high importance both for wired network technologies (Ethernet, InfiniBand etc), and in the field of creating high-speed interchip connections, high-speed memory controllers and peripheral computer buses, since it will allow to improve channel capacity at low computational costs in real-time regime due to the transition to the “above Nyquist speed” regime. Target. Develop an algorithm which has linear computational complexity in the framework of The Resolution Time Theory for frequency-selective communication channels capacity estimation with a linear receiver and PAM-n-signal. Results. An algorithm for estimating specific channel capacity and resolution time is presented, which has linear computational complexity, depending only on the value of the effective memory, for continuous frequency-selective communication channels with a discrete source, in which information is transmitted utilizing bipolar PAM-n-signal. This algorithm has no restrictions on the pulse shape, and the computational complexity linearly depends on the channel memory. The key features of the algorithm are considered, allowing its application in real time. The developed algorithm allows to user fully estimate all the effects caused by data depended jitter. Practical significance. The proposed algorithm makes it possible in real time to select the shape of a partial pulse and the configuration of the signal constellation that increase the specific capacity of a communication system with serial data transmission, including under conditions of transmission in the “Faster than Nyquist” regime.

Inter-Node Message Passing Through Optical Reconfigurable Memory Channel

Inter-Node Message Passing Through Optical Reconfigurable Memory Channel

Introducing packet-level analysis in programmable data planes to advance Network Intrusion Detection

Programmable data planes offer precise control over the low-level processing steps applied to network packets, serving as a valuable tool for analysing malicious flows in the field of intrusion detection. Albeit with limitations on physical resources and capabilities, they allow for the efficient extraction of detailed traffic information, which can then be utilised by Machine Learning (ML) algorithms responsible for identifying security threats. In addressing resource constraints, existing solutions in the literature rely on compressing network data through the collection of statistical traffic features in the data plane. While this compression saves memory resources in switches and minimises the burden on the control channel between the data and the control plane, it also results in a loss of information available to the Network Intrusion Detection System (NIDS), limiting access to packet payload, categorical features, and the semantic understanding of network communications, such as the behaviour of packets within traffic flows. This paper proposes P4DDLe, a framework that exploits the flexibility of P4-based programmable data planes for packet-level feature extraction and pre-processing. P4DDLe leverages the programmable data plane to extract raw packet features from the network traffic, categorical features included, and to organise them in a way that the semantics of traffic flows are preserved. To minimise memory and control channel overheads, P4DDLe selectively processes and filters packet-level data, so that only the features required by the NIDS are collected. The experimental evaluation with recent Distributed Denial of Service (DDoS) attack data demonstrates that the proposed approach is very efficient in collecting compact and high-quality representations of network flows, ensuring precise detection of DDoS attacks.

Neural network-aided receivers for soliton communication impaired by solitonic interaction.

In this paper, different neural network-based methods are proposed to improve the achievable information rate in amplitude-modulated soliton communication systems. The proposed methods use simulated data to learn effective soliton detection by suppressing nonlinear impairments beyond amplifier noise, including intrinsic inter-soliton interaction, Gordon-Haus effect-induced timing jitter, and their combined impact. We first present a comprehensive study of these nonlinear impairments based on numerical simulations. Then, two neural network designs are developed based on a regression network and a classifier. We estimate the achievable information rates of the proposed learning-based soliton detection schemes as well as two model-based benchmark schemes, including the nonlinear Fourier transform eigenvalue estimation and continuous spectrum-aided eigenvalue estimation schemes. Our results demonstrate that both learning-based designs lead to substantial performance gains when compared to the benchmark schemes. Importantly, we highlight that exploiting the channel memory, introduced by solitonic interactions, can yield additional gains in the achievable information rate. Through a comparative analysis of the two neural network designs, we establish that the classifier design exhibits superior adaptability to interaction impairment and is more suitable for symbol detection tasks in the context of the investigated scenarios.

Highly Reliable 3D Channel Memory and Its Application in a Neuromorphic Sensory System for Hand Gesture Recognition.

Brain-inspired neuromorphic computing systems, based on a crossbar array of two-terminal multilevel resistive random-access memory (RRAM), have attracted attention as promising technologies for processing large amounts of unstructured data. However, the low reliability and inferior conductance tunability of RRAM, caused by uncontrollable metal filament formation in the uneven switching medium, result in lower accuracy compared to the software neural network (SW-NN). In this work, we present a highly reliable CoOx-based multilevel RRAM with an optimized crystal size and density in the switching medium, providing a three-dimensional (3D) grain boundary (GB) network. This design enhances the reliability of the RRAM by improving the cycle-to-cycle endurance and device-to-device stability of the I-V characteristics with minimal variation. Furthermore, the designed 3D GB-channel RRAM (3D GB-RRAM) exhibits excellent conductance tunability, demonstrating high symmetricity (624), low nonlinearity (βLTP/βLTD ∼ 0.20/0.39), and a large dynamic range (Gmax/Gmin ∼ 31.1). The cyclic stability of long-term potentiation and depression also exceeds 100 cycles (105 voltage pulses), and the relative standard deviation of Gmax/Gmin is only 2.9%. Leveraging these superior reliability and performance attributes, we propose a neuromorphic sensory system for finger motion tracking and hand gesture recognition as a potential elemental technology for the metaverse. This system consists of a stretchable double-layered photoacoustic strain sensor and a crossbar array neural network. We perform training and recognition tasks on ultrasonic patterns associated with finger motion and hand gestures, attaining a recognition accuracy of 97.9% and 97.4%, comparable to that of SW-NN (99.8% and 98.7%).