Memory Array Research Articles

Implementation of binarized neural networks immune to device variation and voltage drop employing resistive random access memory bridges and capacitive neurons

Resistive Random Access Memories (ReRAM) arrays provides a promising basement to deploy neural network accelerators based on near or in memory computing. However most popular accelerators rely on Ohm’s and Kirchhoff’s laws to achieve multiply and accumulate, and thus are prone to ReRAM variability and voltage drop in the memory array, and thus need sophisticated readout circuits. Here we propose a robust binary neural network, based on fully differential capacitive neurons and ReRAM synapses, used in a resistive bridge fashion. We fabricated a network layer with up to 23 inputs that we extrapolated to large numbers of inputs through simulation. Defining proper programming and reading conditions, we demonstrate the high resilience of this solution with a minimal accuracy drop, compared to a software baseline, on image classification tasks. Moreover, our solution can achieve a peak energy efficiency, comparable with the state of the art, when projected to a 22 nanometer technology.

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical channel-all-around structure are investigated by technology computer-aided design (TCAD) simulation. The simulated drain current–gate voltage (I DS–V GS) curves of the IGZO FeFET show an on–off ratio of up to 107 and a memory window of 1.76 V, proving that ferroelectric hafnium oxide (FE-HfO2) is suitable for a 2T0C transistor. To solve the potential current-sharing problem of the 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of FE-HfO2. This solution shows a remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of the IGZO-based FeFET on 2T0C DRAM memory cells, but also providing an array design guideline for highly reliable 2T0C memory applications.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

Low Operation Voltage, High-Temperature Reliable, and High-Yield BEOL Integrated Hf₀.₅Zr₀.₅O₂ Ferroelectric Memory Arrays

Low Operation Voltage, High-Temperature Reliable, and High-Yield BEOL Integrated Hf₀.₅Zr₀.₅O₂ Ferroelectric Memory Arrays

Heterogeneous integration of spin-photon interfaces with a CMOS platform.

Colour centres in diamond have emerged as a leading solid-state platform for advancing quantum technologies, satisfying the DiVincenzo criteria1 and recently achieving quantum advantage in secret key distribution2. Blueprint studies3-5 indicate that general-purpose quantum computing using local quantum communication networks will require millions of physical qubits to encode thousands of logical qubits, presenting an open scalability challenge. Here we introduce a modular quantum system-on-chip (QSoC) architecture that integrates thousands of individually addressable tin-vacancy spin qubits in two-dimensional arrays of quantum microchiplets into an application-specific integrated circuit designed for cryogenic control. We demonstrate crucial fabrication steps and architectural subcomponents, including QSoC transfer by means of a 'lock-and-release' method for large-scale heterogeneous integration, high-throughput spin-qubit calibration and spectral tuning, and efficient spin state preparation and measurement. This QSoC architecture supports full connectivity for quantum memory arrays by spectral tuning across spin-photon frequency channels. Design studies building on these measurements indicate further scaling potential by means of increased qubit density, larger QSoC active regions and optical networking across QSoC modules.

Behavioral signatures of the rapid recruitment of long-term memory to overcome working memory capacity limits.

Working- and long-term memory are often studied in isolation. To better understand the specific limitations of working memory, effort is made to reduce the potential influence of long-term memory on performance in working memory tasks (e.g., asking participants to remember artificial, abstract items rather than familiar real-world objects). However, in everyday life we use working- and long-term memory in tandem. Here, our goal was to characterize how long-term memory can be recruited to circumvent capacity limits in a typical visual working memory task (i.e., remembering colored squares). Prior work has shown that incidental repetitions of working memory arrays often do not improve visual working memory performance - even after dozens of incidental repetitions, working memory performance often shows no improvement for repeated arrays. Here, we used a whole-report working memory task with explicit rather than incidental repetitions of arrays. In contrast to prior work with incidental repetitions, in two behavioral experiments we found that explicit repetitions of arrays yielded robust improvement to working memory performance, even after a single repetition. Participants performed above chance at recognizing repeated arrays in a later long-term memory test, consistent with the idea that long-term memory was used to rapidly improve performance across array repetitions. Finally, we analyzed inter-item response times and we found a response time signature of chunk formation that only emerged after the array was repeated (inter-response time slowing after two to three items); thus, inter-item response times may be useful for examining the coordinated interaction of visual working and long-term memory in future work.

Overshoot‐Suppressed Memristor Array with AlN Oxygen Barrier for Low‐Power Operation in the Intelligent Neuromorphic Systems

As the demand for bio‐inspired neuromorphic systems grows, memristor has emerged as a pivotal component in artificial synaptic devices. This study delves into the advantages and limitations of the one‐transistor‐one‐resistor (1T‐1R) and 0T‐1R architectures for memory array configurations. A significant enhancement in the memristor's on/off ratio, surpassing 103, achieved by integrating both an overshoot suppression layer (OSL) and an ultra‐thin AlN oxygen barrier layer (OBL) is also reported. The concurrent insertion of an AlOx OSL is essential for manifesting the self‐compliance attribute in 4F2 memristor arrays. Evaluations of a 24 × 24 array embedded with OSL and OBL reveal a substantial reduction in retention variation. In terms of functionality, a 7.13‐fold decline in vector‐matrix multiplication error is observed, accentuating the potential of this approach for neural network synapse applications. The analog reset characteristics of the OBL memristor facilitate over 25 multilevel states. Furthermore, the adoption of nonnegative weights presents an avenue to potentially double synaptic integration density. Through simulation program with integrated circuit emphasis simulations, the necessity of nonnegative and 16‐level quantized conductance in balancing power consumption without accuracy loss at the image classification is validated.

Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection.

Smart healthcare systems integrated with advanced deep neural networks enable real-time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND-type flash memory array with a rounded double channel for computing-in-memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low-power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life-threatening arrhythmias. Incorporated with a simplified spike-timing-dependent plasticity learning rule, the CIM architecture is suitable for robust, area- and energy-efficient in-memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm.

Architecture-level energy model for high-capacity STT-MRAM memory

ABSTRACT Nowadays, STT-MRAM has emerged as one of the leading contenders for next-generation memory technologies. However, STT-MRAM still exhibits high energy consumption due to its peripheral circuits, including the read/write and the sample amplifier (SA) circuits. Therefore, it is crucial to accurately evaluate the energy consumption of memory architectures during the early stages of the design process. Traditionally, energy evaluation can be conducted using the NVSim platform. However, the peripheral read/write circuitry of STT-MRAM undergoes iterative improvements, which cannot be promptly incorporated into NVSim. To addreGss this limitation and to enable comprehensive energy consumption evaluations spanning from device-level to architecture-level for STT-MRAM, an architecture-level energy consumption model is proposed in this paper. The model offers high accuracy and flexibility for the STT-MRAM memory array structure, abstracting the influences of read/write circuits for power evaluations. Comparative analysis is performed between the proposed model and the traditional approaches. When estimating a memory array with 128 × 64, the deviation using the proposed model is less than 2%, showing improved accuracy compared to that with analytical formulas. Notably, the proposed model offers up to 97% time savings in the whole circuit simulation, thus enhancing efficiency in the design and evaluation process.

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

Modeling of Self-Aligned Selector Based on Ultra-Thin Metal Oxide for Resistive Random-Access Memory (RRAM) Crossbar Arrays.

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array.

Atomistic origins of compound semiconductor synthesis with computational neuromorphic engineering

We propose the usage of multi-element bulk materials to mimic neural dynamics instead of atomically thin materials via the modeling of group II–IV compound semiconductor growth using vacancy defects and dopants by creating and annihilating one another like a complex artificial neural network, where each atom itself is the device in analogy to crossbar memory arrays, where each node is a device. We quantify the effects of atomistic variations in the electronic structure of an alloy semiconductor using a hybrid method composed of a semiempirical tight-binding method, density functional theory, Boltzmann transport theory, and a transfer-matrix method. We find that the artificial neural network resembles the neural transmission dynamics and, by proposing resistive switching in small areas with low energy consumption, we can increase the integration density similar to the human brain.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

A fault-tolerant and energy-efficient design of RAM cell and PIM structure in quantum technology

In this paper, a RAM cell in ternary QCA is proposed. Moreover, a 2×1 memory array and a TPIM (ternary processing in memory) structure are designed using the proposed ternary RAM cell. The evaluation of the design parameters shows that the proposed ternary SRAM and PIM structures are efficient in terms of cost, area, and fault tolerance while the volume of information-carrying is high because of the ternary structure. The manufacturing defects in the chemical manufacturing process of QCA circuits are possible. One of these defects is cell omission which has not yet been investigated for QCA-based SRAM in ternary structure. According to the results, by migrating from binary to ternary QCA, the fault tolerance can be increased without increasing the occupied area. Then, the fault tolerance of ternary RAM cells is calculated and compared with that of binary structures. The primary aims of this study are to improve fault tolerance and optimization of design parameters, which are achieved according to the results.

A Memristor Neural Network Based on Simple Logarithmic-Sigmoidal Transfer Function with MOS Transistors

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are potentially applicable in artificial and spiking neural networks, memory arrays, and many other devices and circuits for artificial intelligence. In this paper, a complete electronic realization of an analog circuit model of the modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in the LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an important step towards the forthcoming design of complex memristor-based neural networks for artificial intelligence, for implementation in very high-density integrated circuits and chips.

Insulator Metal Transition-Based Selector in Crossbar Memory Arrays

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials.

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

Programming Operations Analysis and Statistics in One Selector and One Memory Ovonic Threshold Switching + Phase‐Change Memory Double‐Patterned Self‐Aligned Structure

This study explores the reliability of a phase‐change memory (PCM) cointegrated with an ovonic threshold switching (OTS) selector (one selector and one memory [1S1R] structure) based on an innovative double‐patterned self‐aligned architecture. The variability of the threshold voltage () for both the SET and RESET states is examined, comparing different distribution models to validate the use of mean and standard deviation as viable metrics. The dispersion of is tracked under different programming conditions to provide insight into the evolution of device behavior over SET/RESET, endurance cycles, and read cycles. The PCM device is based on a “wall” structure and on Ge2Sb2Te5 alloy, while the OTS is based on a GeSbSeN alloy. The analysis focuses on the programming characteristics and SET pulse optimization, studying current control and pulse fall times. The results are based on statistical data obtained from a kb‐sized memory array. A memory window of over 2 V is achieved. The research helps understanding the DPSA architecture, and PCM + OTS in general, offering insights into their programming, variability, and reliability targeting crossbar applications.

An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.