Programming Operations Analysis and Statistics in One Selector and One Memory Ovonic Threshold Switching + Phase‐Change Memory Double‐Patterned Self‐Aligned Structure

Abstract

This study explores the reliability of a phase‐change memory (PCM) cointegrated with an ovonic threshold switching (OTS) selector (one selector and one memory [1S1R] structure) based on an innovative double‐patterned self‐aligned architecture. The variability of the threshold voltage () for both the SET and RESET states is examined, comparing different distribution models to validate the use of mean and standard deviation as viable metrics. The dispersion of is tracked under different programming conditions to provide insight into the evolution of device behavior over SET/RESET, endurance cycles, and read cycles. The PCM device is based on a “wall” structure and on Ge2Sb2Te5 alloy, while the OTS is based on a GeSbSeN alloy. The analysis focuses on the programming characteristics and SET pulse optimization, studying current control and pulse fall times. The results are based on statistical data obtained from a kb‐sized memory array. A memory window of over 2 V is achieved. The research helps understanding the DPSA architecture, and PCM + OTS in general, offering insights into their programming, variability, and reliability targeting crossbar applications.