A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

Abstract

In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical channel-all-around structure are investigated by technology computer-aided design (TCAD) simulation. The simulated drain current–gate voltage (I DS–V GS) curves of the IGZO FeFET show an on–off ratio of up to 107 and a memory window of 1.76 V, proving that ferroelectric hafnium oxide (FE-HfO2) is suitable for a 2T0C transistor. To solve the potential current-sharing problem of the 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of FE-HfO2. This solution shows a remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of the IGZO-based FeFET on 2T0C DRAM memory cells, but also providing an array design guideline for highly reliable 2T0C memory applications.