Architecture-level energy model for high-capacity STT-MRAM memory

Abstract

ABSTRACT Nowadays, STT-MRAM has emerged as one of the leading contenders for next-generation memory technologies. However, STT-MRAM still exhibits high energy consumption due to its peripheral circuits, including the read/write and the sample amplifier (SA) circuits. Therefore, it is crucial to accurately evaluate the energy consumption of memory architectures during the early stages of the design process. Traditionally, energy evaluation can be conducted using the NVSim platform. However, the peripheral read/write circuitry of STT-MRAM undergoes iterative improvements, which cannot be promptly incorporated into NVSim. To address this limitation and to enable comprehensive energy consumption evaluations spanning from device-level to architecture-level for STT-MRAM, an architecture-level energy consumption model is proposed in this paper. The model offers high accuracy and flexibility for the STT-MRAM memory array structure, abstracting the influences of read/write circuits for power evaluations. Comparative analysis is performed between the proposed model and the traditional approaches. When estimating a memory array with 128 × 64, the deviation using the proposed model is less than 2%, showing improved accuracy compared to that with analytical formulas. Notably, the proposed model offers up to 97% time savings in the whole circuit simulation, thus enhancing efficiency in the design and evaluation process.