Medium Voltage SiC Research Articles

A Review of Partial Discharge in Medium Voltage SiC Power Modules Under Square Wave Excitation: Characterization, Mitigation, and Detection

A Review of Partial Discharge in Medium Voltage SiC Power Modules Under Square Wave Excitation: Characterization, Mitigation, and Detection

Dv/dt Sensing-Based Short-Circuit Protection for Medium-Voltage SiC mosfets

This letter presents a novel short-circuit protection (SCP) for medium-voltage (MV) SiC MOSFETs, that utilizes the turn-on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> of SiC MOSFET within a predetermined interval to monitor SC faults. Unlike conventional methods that detect the fault current/voltage magnitude, proposed turn-on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> detection and protection timing sequence enable a very fast fault response time as well as enhance the noise immunity to fast switching of MV SiC MOSFETs. Furthermore, the proposed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> sensing based SCP can be integrated with DESAT circuit to provide over-current (OC) protection (OCP) under the fault-under-load (FUL) condition. The proposed integrated implementation can respond to SC faults without the blanking-time limitation and eliminates the need for the extra high-voltage sensing capacitor to lower cost. Experimental results on 3.3-kV SiC MOSFETs are provided to validate the effectiveness of proposed SCP method.

SiC Three-Level Neutral-Point-Clamped Converter With Clamping Diode Volume Reduction Using Quasi-Two-Level Operation

Medium voltage (MV) SiC MOSFETs have recently garnered considerable attention in the medium-voltage high-power areas like high-frequency solid-state transformers and multilevel converters. While direct series connection of these MOSFETs is an option for higher voltage levels, it requires complex voltage balancing approaches for device voltage balancing during fast switching transients. Alternatively, converter-level solutions such as the three-level (3L) neutral-point-potential (NPC) converter can be used. This paper proposes a new modulation strategy, combining 3L and Quasi-two-level (Q2L) modulations, to minimize the rating and volume of clamping diodes by tightly controlling the thermal stress on the diodes. This approach achieves better efficiency, higher power density, and a simpler converter bus-structure to stack two SiC MOSFETs effectively in series. We present a real-time clamping diode loss estimation to improve the effectiveness of the proposed modulation strategy. To verify the proposed converter-level approach and modulation strategy, we test a 20 kV rated phase-leg with two 10 kV SiC MOSFETs and 3.3 kV SiC diodes.

Parasitic Capacitive Couplings in Medium Voltage Power Electronic Systems: An Overview

Recent development within the field of medium voltage wide-bandgap semiconductor devices are drawing the attention from both researchers and industries, due to the demanding requirements for more efficient high-power energy conversion. The rapid development has entailed an increased awareness of the negative impact of increased rate of change in voltage, d vd t, and its derived issues caused by the inevitable parasitic capacitive couplings. This paper is dedicated to present an overview of the parasitic capacitive couplings in high-power medium voltage power electronic converter systems, using an example reference system enabled by medium voltage SiC MOSFETs. The definitions of capacitive couplings are presented and the impacts raised by parasitic capacitive couplings are reviewed. In addition, the similarities of different capacitive couplings introduced by components in practical medium voltage systems are presented and summarized. Lastly, the challenges and future work with respect to parasitic capacitive couplings in medium voltage power electronics converter systems are shared from the authors' perspective.

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

From the Measurement of C OSS–V DS Characteristic to the Estimation of the Channel Current in Medium Voltage SiC MOSFET Power Modules

From the Measurement of <i>C</i> _OSS–<i>V</i> _DS Characteristic to the Estimation of the Channel Current in Medium Voltage SiC MOSFET Power Modules

Device Voltage Stress From Ground Leakage Current in Medium-Voltage Solid-State Transformer

Grounding related issues are critical for safe and reliable operation of solid-state transformer (SST) in medium-voltage (MV) applications, e.g., solar photovoltaic and energy storage integration, date center, electric vehicle fast charging, etc. This article presents for the first time the issue of additional device voltage stress due to grounding-loop current in current-source SST, using the soft-switching solid-state transformer (S4T) as an example. The S4T features single-stage isolated ac–ac, ac–dc, or dc–dc conversion with full-range ZVS, derived from flyback converter or current-source converter (CSC). However, the flyback operation for CSC-based SST means that magnetizing current flows through the reverse-blocking devices on only one side of the medium-frequency transformer (MFT) at a time. Then, the voltages across the devices, especially those on the other side of the MFT, can be influenced by parasitic current. A parasitic model of a modular S4T (M-S4T) prototype is developed from direct measurements and datasheets. Using the developed parasitic model and equivalent circuits, the causes of the voltage stress are analyzed. A voltage-stress mitigation scheme of connecting additional grounding capacitors is proposed. Damping resistors are also installed to damp out the grounding-loop resonance. A robust parameter design of the proposed scheme is given. The existence of the voltage stress issue and the effectiveness of the proposed scheme are verified experimentally on an MV SiC M-S4T prototype with inherent parameter variations among the five modules in the prototype. Both single-module and stacked-module operation are demonstrated during steady state and dynamic conditions up to 4 kV peak.

A Low-Voltage Low-Loss Active Reflected Wave Canceller for a Medium-Voltage SiC Motor Drive Based on a Generalized Multilevel Inverter Topology

Multilevel topologies with SiC devices for medium-voltage (MV) motor drive have advantages to reduce the harmonics and device voltage stress and increase efficiency. However, with the application of SiC devices, the reflected wave phenomenon still happens in multilevel motor drives due to its high dv/dt, resulting in overvoltage at motor terminals. This article proposed a T-type circuit-based active reflected wave canceller (ARWC) to suppress the overvoltage of an M-level motor drive with a reduced voltage rating of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {dc}}$ </tex-math></inline-formula> /( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$M-1$ </tex-math></inline-formula> ). A coupled inductor is applied to isolate the ARWC output and the main inverter. In addition, the coupled inductor is designed with a small resistor to allow low current flow into ARWC. The proposed ARWC configuration can be applied for general multilevel topologies. A three-level ANPC converter with a 3.3-kV SiC device is built in the laboratory. A 1.2-kV SiC module is applied in the proposed ARWC. The experimental results at 1.6-kV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {dc}}$ </tex-math></inline-formula> and 16-A (rms) load current with and without proposed ARWC are provided and compared to verify the validity of the proposed method.

Predictive Direct DC-Link Control for 7.2 kV Three-Port Low-Inertia Solid-State Transformer With Active Power Decoupling

Promising for applications including renewable energy and electric vehicle fast charging, a medium-voltage (MV) solid-state transformer (SST) typically has multiple modules series stacked, which requires the modules to be single phase. One critical issue of the single-phase SST is the double-line-frequency power ripple. Traditionally, large passives are used to buffer the ripple, resulting in significantly increased volume and cost. This article for the first time proposes active power decoupling (APD) for the SST and a predictive direct dc-link control method, using a current-source (CS) single-stage SST as an example. An electrolytic capacitorless buffer port is used to absorb the ripple, which tolerates up to a 30% voltage ripple for small capacitance. The APD SST control is challenging. First, the CS SST realizes isolation, dc-link, and multiport in a single stage. Second, different from conventional SSTs or APD converters, the low-inertia dc-link in this SST has a 40% switching ripple, which is difficult to stabilize. To address the control challenge, a direct dc-link control architecture and a predictive control method are proposed. Simulation and experimental results verify the proposed control method on an MV SiC modular soft-switching solid-state transformer (M-S4T) prototype. The proposed APD reduces the SST volume by 53.8%. Importantly, the proposed concept is not limited to the M-S4T, but is generic to other SSTs or APD converters.

A MHz-Pulse-Transformer Isolated Gate Driver With Signal-Power Integrated Transmission for Medium-Voltage SiC MOSFETs

The conventional isolated gate driver (GD) solution for the medium-voltage (MV) SiC <small>mosfet</small> separates the signal and power transmissions and requires a bulky GD power supply (GDPS). This article presents a signal-power integrated GD for MV SiC <small>mosfet</small>s with a compact footprint. The proposed GD transmits both the pulsewidth modulation (PWM) signal and GD power by 20-MHz modulated class-E resonant flyback converters, where the transmitted GD power can maintain constant within the full PWM duty-cycle range (i.e., 0&#x0025;&#x2013;100&#x0025;). In addition, the PWM signal transmission of the proposed GD achieves a low total propagation delay time &lt; 75 ns by utilizing the fast transient of 20-MHz RFCs and the edge-based envelope detector. A printed-circuit-board-based coreless transformer is integrated into the proposed GD to achieve an insulation voltage higher than 10 kV_RMS and a low coupling capacitance of 5.85 pF. The common-mode transient immunity of proposed GD is higher than 100 V&#x002F;ns, which is beneficial to drive MV SiC <small>mosfet</small>s with high <i>dv&#x002F;dt</i>. The proposed GD does not require additional GDPSs nor fiber-optics, which achieves a smaller size compared to conventional isolated GDs and is promising to be integrated into SiC <small>mosfet</small> module packages. Experimental results on 3.3 kV and 10 kV SiC <small>mosfet</small>s are provided to validate the effectiveness of the proposed GD.

Medium Voltage Converter Inductor Insulation Design Considering Grid Requirements

Medium voltage (MV) SiC devices facilitate direct (without 50-/60-Hz transformer) connection of the power electronics converter to the MV grid using simple topology. Compared to the insulation design of MV inductors that have been widely used in the power system, the insulation design of the MV converter filter inductors has new challenges. Particularly, the grid impact on insulation requirements on converter filter inductors is rarely discussed. This article introduces the insulation design of a grid-side filter inductor for a 13.8-kV power conditioning system converter. The grid insulation requirements, including the short-duration power frequency overvoltage and the lightning impulse voltage, are considered in the design. To meet the requirements, the layer-to-layer insulation, winding-to-core/ground insulation, the air gap discharge between the winding and the core, the local electric field, as well as the interturn transient voltage distribution are considered. The designed inductors are validated by the 46 kV (>1 min) dc hi-pot test, 12-kV ac partial discharge test, one-hour single-phase converter full rating test, as well as three-phase converter full rating test.

(Invited) Medium-Voltage SiC Devices for Next Generation of Power Conversion

We report successful demonstration of 3.3kV SiC charge-balanced (CB) JBS diodes and 4.5kV CB MOSFETs with Ron,sp significantly below 1-D SiC unipolar limit. These devices implement a novel scalable drift layer architecture for a high voltage switch as an alternative solution to super-junction devices. Furthermore, 2kV, SiC super-junction (SJ) PiN diodes are reported. These diodes are formed by deep implantation of Al and N and show a blocking voltage 500V higher than comparable non-SJ diodes.

Design and Optimization of a 200-kW Medium-Frequency Transformer for Medium-Voltage SiC PV Inverters

This article presents a design and optimization methodology for a 200-kW medium-frequency transformer (MFT) based on low-loss magnetic core (FINEMET FT-3TL). The proposed optimal design methodology consists of predesign, preliminary design, and optimal design. In the preliminary design, the parallel-concentric winding structure is selected to increase the current carrying capability and reduce the leakage inductance. Based on the parallel-concentric winding concept, a novel cooing and insulation structure with 3-D printed bobbins are proposed. The optimal designed MFT prototype achieves a power density higher than 19.23 kW/L. The electrical insulation system is tested at 12 kV ac peak voltage. In addition, the partial discharge (PD) test is conducted at 7.5 kV ac peak voltage to ensure the PD-free design. The high-frequency bipolar pulsewidth modulation voltage insulation (PD) test is the first time applied in MFT design and test process. Finally, the transformer is applied in a dual-active-bridge (DAB) converter with 200 kW rated power. The peak efficiency of the DAB converter is 99.53%, and the efficiency at 200 kW is 98.85%. The peak efficiency of MFT is 99.844%, and the efficiency at 200 kW is 99.842%.

A Simple Method to Validate Power Loss in Medium Voltage SiC MOSFETs and Schottky Diodes Operating in a Three-Phase Inverter

This paper presents an original method of power loss validation in medium-voltage SiC MOSFET (metal–oxide–semiconductor field-effect transistor) modules of a three-phase inverter. The base of this method is a correct description of the on-state performance of the diodes and the transistors in a PWM (pulse width modulation)-controlled inverter phase leg. Combined electro-thermal calculations are applied to precisely estimate the losses in the power devices and then, to find the suitable circuit parameters of a test circuit to emulate these conditions. A simple square-wave-controlled half-bridge with an inductive load enables the electrical and thermal stresses comparable to these in the inverter, and moreover, provided equations that confirmed the possibility of balancing the load between the diodes and the transistors. The circuit with 3.3 kV SiC MOSFETs was tested to verify the impact of selected parameters on power losses with the main focus on duty ratio. The same module was applied, in addition to an inductive load (3 × 112 μH) and two sets of DC-link capacitors (750 μF), to validate a phase leg of a 220 kVA inverter. In spite of a significantly apparent power, the active power delivered from the DC supply settled around 1 kW, which was enough to emulate 390 W of losses in two transistors and diodes.

Impact of Power Module Parasitic Capacitances on Medium-Voltage SiC MOSFETs Switching Transients

Increased switching speeds of wide bandgap (WBG) semiconductors result in a significant magnitude of the displacement currents through power module parasitic capacitances that are inherent in packaging design. This is of increasing concern, particularly in case of newly emerging medium-voltage (MV) SiC MOSFETs since the magnitude of the displacement currents can be several order higher due to the fast switching transients and increased voltage magnitudes of the SiC MOSFETs compared to their Si counter parts. The severity intensifies when the magnitude of the displacement current becomes comparable to a significant fraction of SiC MOSFETs rated current, leading to the worsened impact on the converter electromagnetic interference (EMI) as well as performance in terms of switching losses. The key objective of this article is to provide a detail insight into the impact of the module parasitic capacitances on the SiC MOSFET switching dynamics and losses. To realize this, a well-defined approach to dissect the switching energy dissipation is proposed, based on which the detailed analysis and quantitative measurements of the module parasitic capacitance impact on terms of added switching energy losses, and common-mode currents are investigated using a custom-packaged 10-kV half-bridge SiC MOSFET power modules. The theoretical analysis and experimental results obtained from dynamic as well as static characterization reveal that the impact of the module parasitic capacitance on the switching energy dissipation is twofold and substantially adverse such that it cannot be overlooked considering its intended application in the high-power MV power electronic converters.

Industrial and Body Diode Qualification of Gen-III Medium Voltage SiC MOSFETs: Challenges and Solutions

In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.

Investigating Impact of Emerging Medium-Voltage SiC MOSFETs on Medium-Voltage High-Power Industrial Motor Drives

The SiC MOSFETs are becoming game-changing devices in the field of power electronics, enabling higher temperatures, power densities, and efficiencies. However, at higher voltages than 1.7 kV, these semiconductors are at early stages of development and yet not commercialized. Based on the characterization results of the state-of-the-art 3.3-kV SiC MOSFETs, for the first time, this paper investigates the design and comparison of topologies commercially used for medium-voltage (MV) drives in 4.16–13.8-kV voltage range in the presence of MV SiC MOSFETs. For this purpose, the cascaded H-bridge, modular multilevel converter, and five-level active neutral point clamped (5-L ANPC) topologies are targeted. Design is carried out at 4.16-, 6.9-, and 13.8-kV voltages (4.16 and 6.9 kV in the case of 5-L ANPC) and 3- and 5-MVA power ratings using commercial Si IGBTs as well as latest generation noncommercial 3.3-kV SiC MOSFETs, in order to enable investigation of impact from the emerging MV SiC MOSFETs on motor drive system. Selection of several voltage and power levels is to elucidate behavior of converters at a different voltage and power rating and determine the best option for given operating point. Based on design data, comparisons are done among the mentioned topologies from different points of view including efficiency, passive component requirement, semiconductor utilization, power density, low-speed operation capability, fault containment, and parts count. Experimental results on an H-bridge cell made with 3.3-kV SiC MOSFETs are brought to verify converter modeling in MATLAB environment as well as the conveyed thermal calculations.

Solid-State Transformer and MV Grid Tie Applications Enabled by 15 kV SiC IGBTs and 10 kV SiC MOSFETs Based Multilevel Converters

Medium-voltage (MV) SiC devices have been developed recently which can be used for three-phase MV grid tie applications. Two such devices, 15 kV SiC insulated-gate bipolar transistor (IGBT) and 10 kV SiC MOSFET, have opened up the possibilities of looking into different converter topologies for the MV distribution grid interface. These can be used in MV drives, active filter applications, or as the active front end converter for solid-state transformers (SSTs). The transformerless intelligent power substation (TIPS) is one such application for these devices. TIPS is proposed as a three-phase SST interconnecting a 13.8 kV distribution grid with a 480 V utility grid. It is an all SiC device-based multistage SST. This paper focuses on the advantages, design considerations, and challenges associated with the operation of converters using these devices keeping TIPS as the topology of reference. The efficiency of the TIPS topology is also calculated using the experimentally measured loss data of the devices and the high-frequency transformer. Experimental results captured on a developed prototype of TIPS along with its measured efficiency are also given.

Medium Voltage Hybrid Si IGBT/SiC JBS Diode Module Development

Medium voltage SiC Junction Barrier Schottky (JBS) diodes are considered as a replacement for conventional Si freewheeling PiN diodes in phase-leg applications. While lower voltage SiC Schottky diodes are commercially available, medium voltage SiC JBS diodes are also attractive due to their relative simplicity and thus potential for low cost. In this work, the performance of 4.5 kV SiC JBS diodes paired with Si IGBTs is reviewed and compared to legacy components. Hybrid Si/SiC module design and performance are reviewed and potential reliability issues are examined.