Maximum Clock Rate Research Articles

A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset

A novel direct digital frequency synthesizer (DDFS) based on a parabolic polynomial with an offset is proposed in this paper. A 16-segment parabolic polynomial interpolation is adopted to replace the traditional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less structure such that the speed can be significantly improved. This work is manufactured by a standard 0.13 μm CMOS cell-based technology. The maximum clock rate is 161 MHz, the core area is 0.33 mm2, and the spurious free dynamic range (SDRF) is 117 dBc by physical measurements on silicon.

HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case M = 2). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers.

A double data rate architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

Switching dynamics in non-volatile polymer memories

The time dependence of resistive switching in metal-metal oxide-organic semiconductor-metal diodes is investigated. The switching dynamics is controlled by two intrinsic time dependences. A single switching event occurs in a time scale of 400 nanoseconds, but the maximum repetitive switching between ON- and OFF-states is limited by a “dead time” of a few milliseconds. The dead time is the waiting time after programming in which a next switch is inhibited. Therefore, fast repetitive pulsing prevents the observation of non-volatile switching and limits the maximum clock rate at which these memories can be used. Understanding the origin of this dead time is crucial to future memory applications. Furthermore, the occurrence of a dead time is possibly the origin of the huge variation in the reported switching times.

Design and Implementation of Subspace-Based Speech Enhancement Under In-Car Noisy Environments

In this paper, a new subspace-based speech enhancement model is presented for in-car speech enhancement. To effectively suppress background noise, this model incorporates a perceptual filterbank and an auditory gain adaptation derived from a psychoacoustic model into a signal subspace approach. The projection approximation subspace tracking deflation (PASTd) algorithm is used to track the signal subspace. For real-time processing, a system-on-a-programmable-chip architecture and a very large scale integration design of the PASTd algorithm are proposed. To realize a pipeline computation, this paper presents a pipelined PASTd architecture without data-dependent hazards. The maximum clock rate is 9.7 MHz, and the typical clock rate, which achieves the real-time requirement, is 4.6 MHz. The corresponding architecture was experimentally verified via an ALTERA EPXA10 development board.

Nano/CMOS architectures using a field-programmable nanowire interconnect

A field-programmable nanowire interconnect (FPNI) enables a family of hybridnano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid)approach proposed by Strukov and Likharev, allowing for simpler fabrication,more conservative process parameters, and greater flexibility in the choice ofnanoscale devices. The FPNI improves on a field-programmable gate array (FPGA)architecture by lifting the configuration bit and associated components out of thesemiconductor plane and replacing them in the interconnect with nonvolatile switches,which decreases both the area and power consumption of the circuit. This is anexample of a more comprehensive strategy for improving the efficiency of existingsemiconductor technology: placing a level of intelligence and configurability in theinterconnect can have a profound effect on integrated circuit performance, and can beused to significantly extend Moore’s law without having to shrink the transistors.Compilation of standard benchmark circuits onto FPNI chip models shows reduced area(8 × to 25 ×), reduced power, slightly lower clock speeds, and high defect tolerance—an FPNIchip with 20% defective junctions and 20% broken nanowires has an effectiveyield of 75% with no significant slowdown along the critical path, compared toa defect-free chip. Simulations show that the density and power improvementscontinue as both CMOS and nano fabrication parameters scale down, althoughthe maximum clock rate decreases due to the high resistance of very small(<10 nm) metallic nanowires.

Hardware implementation of a sub-pixel algorithm for real-time saw blade deflection monitoring

Deflections of saw blades during timber sawing process due to tension loss lead to downgrading and value loss of timber. In this paper a CCD-type laser triangulation sensor is used to monitor the saw blade deflections. Deflections monitoring has to be done in real-time which compels the necessity to use efficient algorithm with low computational cost. High speed algorithm that makes use of an approximated centre of gravity (COG) and an overall peak-to-peak amplitude methods has been designed and implemented in a Field Programmable Gate Array (FPGA). The approximated COG method tracks the position of the saw blade in real-time. It generates results at 7000 frames/s at the sensor's maximum clock rate of 2 MHz. It also provides a sub-pixel resolution of 1/8 pixel. The overall peak-to-peak amplitude method determines the deflection level of the saw blade based on its recorded positions. Both methods are simple to implement and require low resource usage, while providing reliable real-time results.

A high-speed optical mark reader hardware implementation at low cost using programmable logic

In today's fast-paced information-driven society, the need for accurate, timely, and cost-effective data collection is very critical. Optical mark reader (OMR) systems can be used to achieve these aspects. This paper describes the development of a low-cost and high-speed OMR system prototype for marking multiple-choice questions. The novelty of this approach is the implementation of the complete system into a single low-cost Field Programmable Gate Array (FPGA) to achieve the high processing speed. Effective mark detection and verification algorithms have been developed and implemented to achieve real-time performance at low computational cost. The OMR is capable of processing a high-resolution CCD linear sensor with 3456 pixels at 5000 frame/s at the effective maximum clock rate of the sensor of 20 MHz (4×5 MHz). The performance of the prototype system is tested for different marker colours and marking methods. At the end of the paper the proposed OMR system is compared with commercially available systems and the pro and cons are discussed.

Hardware-driven adaptive k-means clustering for real-time video imaging

A new adaptive k-means clustering algorithm for real-time video imaging is presented. In the proposed solution, a weighted contribution of both pixel intensity and distance between the pixels is used for cluster identification. The weight adaptation of each parameter reduces the computation complexity and makes it possible to implement the algorithm in hardware. The algorithm is designed for real-time video imaging in a VLSI implementation. It was implemented with 15 kgates and maximum clock rate of 80 MHz. Simulation results prove that a QCIF image could be handled in 15 f/s.

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.

SiGe HBT/BiCMOS Technologies and their Applications to Communication ICs/LSIs

ABSTRACTSelf-aligned ultra-high-speed SiGe HBTs were developed by using selective epitaxial growth (SEG) technology. The use of HCl-free SEG, incorporation of C, and optimization of doping profiles significantly improves the performance of the HBT, producing a transistor with a high cutoff frequency of 170 GHz and a maximum oscillation frequency of 204 GHz, for a minimum ECL gate delay time of 4.8 ps. This is applied in a 16:1 MUX with a maximum clock rate of 57 GHz. A 0.13-μm SiGe BiCMOS technology is also realized without any degradation of CMOS due to the high stability of SiGe HBTs. Furthermore, the structure of SiGe HBT is optimized for an emitter scaled down towards 100 nm, mainly through the use of a funnel-shaped emitter electrode to reduce both emitter and base resistances. High-speed operation of a static frequency divider demonstrates the advantage of SiGe HBTs for ultra-high-speed communications systems.

Hardware-Software Implementation of MPEG-4 Video Codec

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

A high-speed subpixel edge detector implementation inside a FPGA

In this paper we present a field programmable gate array (FPGA) implementation of a real-time subpixel edge detector. In comparison to existing edge detectors, the proposed method is implemented in hardware and its computational cost and complexity are very low. This in turn reduces the overall system cost quite significantly. The edge detection method is based on the approximation of the edge profile with a first-order linear function and then extrapolating the line to intercept a constant function. The position where both lines intersect will be the edge position. The detector is capable of processing a high-resolution CCD linear sensor at 2000 frames/s at the maximum clock rate of the sensor of 2 MHz. For that reason it is as fast as an analogue approach. The experimental results show that the proposed method can increase the resolution of an existing intelligent line camera by a factor of 6 or more. From the above it can be concluded that the proposed edge detector is effective for real-time, low-cost subpixel edge detection.

High-speed and low-power split-radix FFT

This paper presents a novel split-radix fast Fourier transform (SRFFT) pipeline architecture design. A mapping methodology has been developed to obtain regular and modular pipeline for split-radix algorithm. The pipeline is repartitioned to balance the latency between complex multiplication and butterfly operation by using carry-save addition. The number of complex multiplier is minimized via a bit-inverse and bit-reverse data scheduling scheme. One can also apply the design methodology described here to obtain regular and modular pipeline for the other Cooley-Tukey-based algorithms. For an N(= 2/sup n/)-point FFT, the requirements are log/sub 4/ N - 1 multipliers, 4log/sub 4/ N complex adders, and memory of size N - 1 complex words for data reordering. The initial latency is N + 2 /spl middot/ log/sub 2/ N clock cycles. On the average, it completes an N-point FFT in N clock cycles. From post-layout simulations, the maximum clock rate is 150 MHz (75 MHz) at 3.3 V (2.7 V), 25/spl deg/C (100/spl deg/C) using a 0.35-/spl mu/m cell library from Avant!. A 64-point SRFFT pipeline design has been implemented and consumes 507 mW at 100 MHz, 3.3 v, and 25/spl deg/C. Compared with a radix-2/sup 2/ FFT implementation, the power consumption is reduced by an amount of 15%, whereas the speed is improved by 14.5%.

Simulation of time evolution of clocked and nonclocked quantum cellular automaton circuits

We have studied, by means of a Monte Carlo simulation, data propagation in quantum cellular automaton circuits, comparing the performance of nonclocked and clocked implementations. Based on two choices of fabrication parameters, we have evaluated the maximum achievable clock speed for different operating temperatures, concluding that better performance can be obtained with the clocked architecture, which, however, involves significant technological difficulties. The large discrepancy existing between a simple estimate of the cell switching time, based on the RC time constant, and our results is discussed and explained by means of an intuitive argument. Two different circuits have been investigated, a binary wire and a majority voting gate, obtaining analogous results, with a slightly smaller maximum clock rate for the majority voting gate, due to the larger number of cells involved.

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBT technology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology.

A VLSI chip implementation of an A/D converter error table compensator

Error table compensation can be used to improve the spurious free dynamic range performance of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, additional on-chip circuits including delays and an adder, and a lookup table that is stored in external memory. The cascadable 10GOPS transversal filter differentiator chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti-symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4–2 compressors to reduce the transistor count. The chip was fabricated in a 0.35-μm CMOS process, measures 3.1×4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz. It is shown that the error table compensation system is capable of providing between 7 and 13 dB improvement in the dynamic range of typical high-speed A/D converters.

Delta-Sigma Waveguides for Music Synthesis

33 Computer Music Journal, 23:4, pp. 33–47, Winter 1999 © 1999 Massachusetts Institute of Technology. Physical modeling of musical instruments has proven to be an interesting and useful technique for sound synthesis, because it provides the variability of real instruments. Natural dynamics can be captured in the model, yielding realistic emulation of traditional instruments. Model parameters can correspond to actual physical parameters so that parameter adjustment is intuitive, and these parameters can be adjusted to produce exotic new sounds. The digital waveguide (Smith 1992) is a computationally efficient method for the physical modeling of strings, drum heads, bores, and other resonant structures that appear in musical instruments. These waveguides can be implemented as a program running on a general-purpose computer which generates and stores sounds for later playback. Computers with sufficient capabilities can generate some of these sounds in real time for playing the sounds as they are produced. Alternately, special-purpose computer hardware can implement these waveguides to produce the sounds in real time. Recent work has introduced the possibility of digital hardware that can be reconfigured, and this alternative implementation may be particularly attractive for music synthesis. The reconfigurable hardware offers operating performance that approaches that of specialized, dedicated devices. However, the hardware can also be rearranged to implement different processing structures. The time required to rearrange the hardware is typically long with respect to the processing time while in any particular configuration, but this constraint appears to be consistent with typical music synthesis systems; that is, flexibility of synthesis is desired, but some delays can be tolerated to “patch” new sounds. The reconfigurable hardware does impose certain implementation constraints when compared with software emulations running on a generalpurpose computer. These constraints are similar to those associated with any hardware implementation of physical models. This article addresses the constraints and shows accommodations that support the use of reconfigurable devices to implement digital waveguides. A direct pulse-code modulated (PCM) implementation of a digital waveguide in hardware leads to underutilization of hardware resources in two significant ways. First, the hardware data paths are clocked at rates near the audio rate of 44.1 kHz, which is significantly below the maximum clock rate typical for modern digital circuits. Second, the wide PCM data paths require large coefficient multipliers in the filter. A delta-sigma approach can be used to produce a more efficient implementation, with the recirculated data reduced to a high-speed stream of single bits. This filter hardware is significantly smaller, because multiplication of a coefficient by a single bit in the stream can be implemented as a multiplexer.

Full-scale integration of superconductor electronics for petaflops computing

Ultralow-power and ultrahigh-speed single-flux-quantum electronics is an enabling technology solution for near-term petaflops computing. The proposed hybrid technology multithreaded (HTMT) petaflops-scale computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Pbits s-1. In this frequency regime, on-chip interconnect mimics the system interconnect problem. On-chip latency can be minimized with increased gate density by using more levels of metal and smaller line pitch. This may be even more important than increasing the maximum clock rate by using smaller junctions and higher critical current density. Superconductor ICs at an integration level of 100k gates cm-2 are proposed for the processors, first-level cache and interprocessor network. Petaflops capacity will require a compact, optimized system-level packaging strategy to achieve the necessary computational density and interconnect bandwidth. Modular packaging and automated circuit testing are required to minimize manufacturing costs. We focus on the critical technology challenges that exist for the IC foundry, packaging and the I/O data link and present technology roadmaps to achieve the HTMT requirements.

A reentrant delay-line memory using a YBa/sub 2/Cu/sub 3/O/sub 7-δ/ coplanar delay-line

The rapid growth in telecommunication traffic demands a higher-speed asynchronous transfer mode (ATM) switching system. At present, the upper limit of the system clock rate is determined by the maximum clock rate of conventional semiconductor memory devices, such as the register files used in ATM cell buffer storage. This is because the maximum clock rate of these register files is restricted by the propagation delay time between each register stage. Since a reentrant superconducting delay-line memory avoids this restriction using an analogue delay given by the superconducting delay line, we have proposed that this memory should be used in high-speed ATM cell buffer storage. Recently, we fabricated a 10-/spl mu/m-wide 37-cm-long YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// coplanar delay-line. This line had a delay of approximately 2.8 ns. Using this coplanar delay-line and an assembly of commercially available integrated circuits, we successfully developed superconducting delay-line memory. This memory operates as a 32-bit buffer storage at a clock rate of 10 GHz, which is several times faster than the register files. This result shows that the superconducting delay-line memory is a powerful candidate for high-speed ATM cell buffer storage.